The Phase-2 ATLAS ITk Pixel Upgrade

Transcription

1 The Phase-2 ATLAS ITk Pixel Upgrade T. Flick (University of Wuppertal) - on behalf of the ATLAS collaboration 14th Topical Seminar on Innovative Particle and Radiation Detectors () October 2016 Siena

2 Overview now phase 2: 2024/25 LHC Upgrade towards High Luminosity LHC (HL-LHC) in (phase 2) ATLAS will replace its inner detector completely New all-silicon Inner Tracker (ITk), inner part pixels, outer part strips (see next talk by Afroditi Koutoulaki) In this presentation: Motivation Layout options (short view) FE-electronics and sensor development Powering scheme and its protection chip Readout architecture and data transmission scheme 2

3 ATLAS Phase-2 Upgrade Motivation 2024: LHC will become High Luminosity-LHC to produce 3000 fb -1 integrated luminosity until 2035 ( precision measurements and studies of rare processes). Instantaneous luminosity increase by factor 5-7 (particle density) up to 5*10 34 cm -2 s -1 Integrated luminosity increase by factor 10 (radiation damage) LHC: 25 vertices HL-LHC: 200 vertices Higher track density better tracking granularity Higher particle flow higher radiation damage (current components already damaged by 2024) LHC: 25 vertices HL-LHC: 200 vertices install new inner tracker (ITk) 3

4 Slim stave I-Beam stave Layout Options (Pixel View) Pixel / Strips Extended η=4.0 Inclined η=4.0 Two main layout options are under discussion: Conventional design: barrel + rings Inclined design: tilted modules at end of staves + rings 5 Pixel barrel layers plus end-cap ring structure Coverage up to ƞ=4.0 9 space points per track Innermost barrel-layer will have double-chip modules, outer barrel layers and rings/disks have quad-chip modules Around FE-chips in modules will be mounted conventional inclined 4

5 Front-end Electronics 3.5 mm New FE-Chip based on RD53 development: RD53 FE-I4 technology 65 nm 130 nm Pixel dimension 50 µm x 50 µm 50 µm x 250 µm # of pixels ~ chip dimension 18 mm x 20 mm 19 mm x 20 mm hit rate 3 GHz/cm GHz/cm 2 in-time threshold < 1000 e < 4000 e typ. noise (ENC) < 100 e < 300 e bandwidth 5 Gb/s 160 Mb/s rad. hardness > 5 MGy > 2.5 MGy Digital Sea Analog Island (4x) FE65-P2 4.2 mm A first RD53 test-chip in hand (general purpose for ATLAS & CMS): FE65-P2 Tests ongoing Large-scale prototype (RD53A chip) to be submitted in March 2017 Using a future chip based on RD53 developments is baseline, to be used with different kinds of sensors (planar, 3D, passive/active CMOS?) RD53A 5

6 First measurements of FE65-P2 connected to Sensor FE65-P2 module has been built and tested (64x64 pixel matrix) connected to planar sensor from Hamamatsu Measurements: Threshold tuned to 800 e - Noise measurement: < 40 e - Noise with sensor: increases only slightly w.r.t. bare chip Irradiation and beam measurements show good functionality of the prototype Row Occupancy after 20 s in beam Hits Row MeV proton tracks (45 incidence) TOT 0 some unconnected pixels Col Col 6

7 Sensor Development Planar Quadchips Three development strains ongoing: planar sensors 3D sensors CMOS technology (new technology) 3D column design Intensive sensor development program ongoing with different vendors (for each of the technologies) Currently the actual pixel FE chip (FE-I4) is used for testing: 4 chip modules have been mounted and tested CMOS as a new technology is undergoing a demonstrator program to show feasibility until early next year Small size prototypes bonded or glued to FE-I4 Full size prototypes bonded or glued to FE-I4 Fully monolithic large size demonstrator CMOS pixel 7

8 Planar Sensors 4 chip sensors, ganged and long pixels in inter-chip regions Different techniques to reduce the inactive edges: slim edges or even active edge designs Study of various topics: Efficiency, irradiation, very thin sensor bulks (50 µm), high eta efficiency, power dissipation, etc. Test devices show very good behavior (tested with IBL FE-I4 chips) Fully working modules, good HV stability The possible range of operation bias voltage for a pixel module with a 100 µm thick sensor is V after irradiation up to 1x10 16 n eq /cm 2 The resulting power dissipation at V is ~25-50 mw/cm 2 50µm Efficiency Pixel Map 250µm IV-curves edge-efficiency 8

9 3D Sensors Prototype runs for FE-I4 dimensions 50µm perpendicular incidence (50 µm x 250 µm) tested in lab, test beams, and for irradiation hardness good performance observed 250µm Hit collection efficiency of around 97-99% observable, dependent on incidence angel also after irradiation to high level New batches with small pitches (50 µm x 50 µm) under test show good performance as well Investigating different production techniques and sensors thicknesses (single sided production, SOI, column variants, UBM) Substrate thicknesses of around µm can be realized Test of ITk geometry and RD53 chip structures are foreseen Pixel Cell Design 9

10 Powering Scheme Powering will be serial, to reduce cable needs Serial powering setup installed in Bonn 6 modules mounted on double sided stavelet FE-I4 based quad modules Tests show a comparable functionality between parallel and serial powering Threshold and noise Noisy modules lead to a negligible higher noise in other modules (5 e - ) Full chain can be operated safely Dummy BNQ01 BNQ00 BNQ05 HV Cooling Power CLK, CMD, Data, NTC 10

11 Pixel Serial Powering Protection Chip (PSPP) Serial powering is supplying a complete module chain by one line Need to prevent chain failure due to single module failure Bypass chip (PSPP) has been developed, being placed in parallel to each module Capable of bypassing each module in case of failure Overvoltage protection Controller chip communicates via I2C-HC to the PSPP s in order to switch manually Separate control and power line for PSPP chip I SP + HV Readout I SP - M1 FE FE FE FE M2 FE FE FE FE Mx-1 FE FE FE FE Mx FE FE FE FE needed, but lots of cables saved with this powering scheme To computer End-of-Stave Board Controller Chip PSPP Chip PSPP Chip PSPP Chip PSPP Chip PSPP power Cooling pipe 11

12 Readout Connection between on- and off-detector via electrical-optical link: Currently defining opto-converter location innermost layer: ~10 MGy!) From FE-chip to end of inner detector electrically (5-7 m) 1 m 5-7 m 80 m Then optically towards the off-detector electronics (~80 m) Around links needed: Downlink: likely to be done using a CERN commonly developed GigaBit- Transceiver (GBT) carrying 16x 160 Mb/s links towards modules well within the chip s capability. Uplink: Large bandwidth spread between inner and outer layer: 5 Gb/s per FE for innermost layer (3.3 Gb/s for innermost ring) 640 Mb/s per FE for outer layer (1 Gb/s for outermost ring) Combining lines would be desirable in terms of material. Low mass and high data rate is needed tricky! We are looking into different options how to drive out data fast enough in good quality 12

13 Micro Wires and Flexes Cables have been tested up to ~6 Gb/s transmission rate successfully: Flex cables ~1m Twisted pair ~1m TwinAx cables ~6m Flex cables (on-stave) 0.7 mm 1.1 mm 1.25 mm TwinAx cable AWG30 (off-stave) 1.95 mm Signal manipulation and balancing needed to reach these rates pre-emphasis, equalization, 8b/10b or 64b/66b encoding Also hybrid twisted pair (1 m) to TwinAx (5 m) has been tested Twisted pair cable AWG36 (on-stave) up to 5 Gb/s as well some cable properties: Flex 0.25 mm width % X/X0 Twisted Pair AWG 36 : mm 0.02% X/X0 TwinAx AWG 30 : mm 0.07% X/X0 Hybrid solution TwinAx to twisted pair cables 13

14 Conclusion & Outlook In 2024 (Phase-2) ATLAS will install a new all-silicon inner tracker (ITk). Currently there is lots of R&D ongoing in all the various fields: Layout and mechanics Sensors and FE-Chip Powering and protection Readout ASIC and sensor prototypes under testing. Test setups using FE-I4 (current ATLAS pixel chip) in various labs for testing. New FE-chip prototype submission foreseen for early Tests with ITk like sensor tiles envisaged. ITk Pixel TDR to be written by end of There is a big R&D going on. We will narrow down the options in the coming year to have a baseline design for the TDR by end of next year. 14

15 Thank you for your attention! 15

16 CMOS Demonstrator Program Passive CMOS sensor + R/O chip Study charge collection Passive sensor for hybrid detector Possible cost advantage if performance is the same as traditional sensor Active CMOS sensor + R/O chip CCPD hybrid detector Possible on-sensor functionality like sub-pixel encoding Active CMOS sensor with standalone R/O DMAPS Depleted Monolithic Active Pixel Sensor Significant cost reduction Suitable for outer layers Several chips and vendors under test Test-beam measurements and chip qualification ongoing Demonstrator by end of this year 16