Engineer-to-Engineer Note

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1 Engineer-to-Engineer Note EE-312 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources nd or e-mil or for technicl support. Building Complex VDK/LwIP Applictions Using Blckfin Processors Contributed by Kushl Snghi Rev 1 Mrch 2, 2007 Introduction Anlog Devices, Inc. offers port of the light-weight TCP/IP (LwIP) stck for the Blckfin fmily of embedded processors. The LwIP stck on Blckfin processors cn be used to develop n embedded networking ppliction in combintion with n udio/video or n industril utomtion/control ppliction. LwIP is n ttrctive utility tht llows you to quickly port stndlone embedded ppliction to networked embedded ppliction. Severl steps re necessry in the integrtion process in order to produce highly efficient nd robust ppliction. This document provides guidelines to integrte LwIP with other system peripherls or pplictions to minimize common pitflls in designing LwIP-bsed pplictions on Blckfin processors. This document lso discusses system optimiztion techniques tht mximize the performnce of pplictions integrted with LwIP on Blckfin processors. The processor resources utilized by the LwIP port re lso described to help you design n efficient system. 1 Motivtion Embedded networking pplictions re now incresingly gered towrd trnsmitting multimedi content over wired or wireless networks. Industril utomtion nd control pplictions re other res where dding network cpbility is desirble. Figure 1 shows pplictions in which Internet connectivity is desired. Anlog Devices offers roylty free (under license greements) softwre building blocks to id in fster development of complex embedded networking pplictions. The following is list of essentil nd bsic softwre components tht re vilble with Anlog Devices processor development environment suite, VisulDSP nd higher: LwIP A light-weight TCP/IP stck [1] ported to ADSP-BF53x nd ADSP-BF56x processors 1 Device drivers nd system services librries (SSLs) API functions for configuring nd mnging system resources nd peripherl devices [10]. VisulDSP++ Kernel (VDK) [13] A rel-time kernel. Use this low-resource kernel to efficiently mnge system resources in multi-tsking ppliction environment. 1 The LwIP stck is not vilble on ADSP-BF535 Blckfin processors. Copyright 2007, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 MM SDK Multimedi Softwre Development Kit [14]. This includes code exmples of common relworld multimedi pplictions. Home Networking - DVD plyers/receivers/spekers/ IPTv, IP phone Internet Industril utomtion/control Network Web Cmers, Surveillnce Figure 1. Typicl Embedded Networking Applictions A rel-world embedded networking ppliction my involve the integrtion of these softwre building blocks into system. The integrtion of different softwre components my cuse severl softwre nd hrdwre resource conflicts. In ddition, the use of softwre components with such high level of bstrction on resource constrined embedded pltform my led to under-utiliztion nd mismngement of system resources. This EE-Note specificlly describes severl spects of integrting LwIP with the softwre components described bove. Following the procedures described in this document will id you in fster development of LwIP-bsed pplictions on Blckfin processors. The reminder of the document is orgnized s follows: Section 2 provides n overview of LwIP. Section 3 discusses benchmrk results nd memory requirements for LwIP on Blckfin processors. Section 4 discusses softwre nd hrdwre guidelines for integrting LwIP with other pplictions. Section 5 describes optimiztion techniques specific to the Blckfin pltform to help you increse system nd core performnce. This EE-Note is not substitute for the LwIP mnul, VDK mnul, system services mnul, or other relted documenttion [1] [2] [3] [4] [5]. Building Complex VDK/LwIP Applictions Using Blckfin Processors (EE-312) Pge 2 of 12

3 2 LwIP Overview LwIP is light-weight implementtion of the TCP/IP protocol stck. LwIP is free nd open source softwre vilble for downlod from Due to its low memory requirements, LwIP is suitble for embedded pplictions. Detiled informtion on LwIP my be obtined from LwIP hs been ported to ADSP-BF53x nd ADSP-BF56x processors, nd the port is vilble with the VisulDSP++ development toolset. To strt developing TCP/IP ppliction on Blckfin processors, you cn use the ADSP-BF537 EZ-KIT Lite development system, which hs dedicted Ethernet interfce. For ADSP-BF533/BF532/BF531 nd ADSP-BF561 processors, you cn use the USB-LAN extender crd. For detils on how to get strted building TCP/IP project, refer to the LwIP User Guide [1]. The LwIP port to Blckfin uses the VisulDSP kernel (VDK) nd the device drivers (DD) nd system services librries (SSL). Refer to [10] for VDK documenttion nd to [7] for system service librries documenttion. 3 LwIP Resource Usge on Blckfin Processors This section discusses the throughput, memory requirements, nd system resources utilized in the execution of LwIP on Blckfin processors. 3.1 Throughput for LwIP on Blckfin Processors The throughput for the LwIP port ws mesured on Blckfin using the ADI-TTCP tool dpted from freely vilble PCATTCP tool. The detils of the tool re discussed in ADI-TTCP.doc, which is locted in the ccompnying.zip file [21]. Figure 2 shows pek throughput versus buffer size for LwIP on the ADSP-BF537 pltform. Note tht the indicted results my vry, bsed on network trffic nd the supported bndwidth on the network. As shown in Figure 2, LwIP supports up to 11 Mbyte/s of throughput for the TCP nd the UDP protocol stck. Pek throughput vs Buffer size Mbyte/s Buffer size (Bytes) TCP Red TCP Write UDP Red UDP Write Figure 2. Buffer Size vs. Pek Throughput Building Complex VDK/LwIP Applictions Using Blckfin Processors (EE-312) Pge 3 of 12

4 3.2 Memory Footprints of LwIP on BF53x Processors As mentioned bove, the LwIP port uses VDK nd the system services librries (SSLs). The memory footprint is divided individully mong these components to obtin better estimte when integrting softwre components or projects tht lredy use one of these components. Note tht the numbers re pproximte vlues nd were derived from simple Hello world progrm run on LwIP. Softwre Component/Protocol UDP (code) TCP (code) UDP (dt) TCP (dt) LwIP 35kB 52kB 10kB 12kB System Service lib 15kB 15kB 1.2kB 1.2kB VDK lib + miscellneous 28kB 28kB 43kB 43kB Totl 78kB 95kB 54.2kB 56.2kB Tble 1. Code nd dt memory footprints for n LwIP-bsed ppliction Appliction Type Driver buffers Heps (KB) Defult Rx = 8 * 1560 Tx = 2 * 1548 ~16KB Memory pool (KB) Pcket buffers (KB) Totl size (KB) ~64kB ~7kB ~64kB ~151kB Applictions (Audio/ Video) (Lrge pcket size) Smll Applictions (Control Applictions) (Smll pcket size) Rx = 16 * 1560 Tx = 8 * 1560 ~50KB Rx = 8 * 256 Tx = 8 * 256 ~4KB ~128kB ~7kB ~128kB ~313kB ~8kB ~7kB ~8kB ~27kB Tble 2. Hep re requirements for LwIP 3.3 Other Required System Resources Interrupts nd DMA When using LwIP on ADSP-BF537 processors, the drivers use the dedicted Ethernet controller. By defult, the Ethernet DMA is mpped to IVG11 for which there is dedicted DMA chnnel. For ADSP-BF533/BF532/BF531 nd ADSP-BF561 processors, LwIP uses the USB-LAN extender crd. By defult, the device driver uses single interrupt level for frme reception nd trnsmit completion. IVG8 is used on ADSP-BF533 processors s the host interrupt level, nd IVG11 is used on ADSP-BF561 processors. Refer to [3] [4] for dditionl informtion on device driver design. Building Complex VDK/LwIP Applictions Using Blckfin Processors (EE-312) Pge 4 of 12

5 4 Softwre nd Hrdwre Guidelines 4.1 Softwre Guidelines LwIP is ported to Blckfin on VDK pltform. It is expected tht users of LwIP re fmilir with generl rel-time operting system (RTOS) concepts. A discussion of detiled RTOS concepts is not in the scope of this ppliction note. Refer to [13] for generl RTOS concepts. This section lists nd describes common softwre conflicts tht my rise when integrting LwIP with other softwre components or pplictions. At minimum, ny softwre component tht involves the use of system service librries will require the use of interrupts nd the DMA mnger. Integrting two or more projects tht use system services librries requires one interrupt nd DMA mnger for the entire ppliction. This is lso true for the device mnger or deferred cllbck mnger nd ll services used within the system. Integrting more devices or resources into the system requires dditionl memory lloction for the device driver mnger nd interrupt mnger. The following listing shows the mcros used to ssign memory for DMA chnnels nd devices. Use n pproprite multipliction fctor, bsed on the number chnnels/devices used within the system. // DMA Mnger dt (bse memory + memory for 2 DMA chnnels) sttic u8 DMAmgr_storge[ADI_DMA_BASE_MEMORY + (ADI_DMA_CHANNEL_MEMORY * 2)]; // Device Mnger dt (bse memory + memory for 2 devices) sttic u8 devmgr_storge[adi_dev_base_memory + (ADI_DEV_DEVICE_MEMORY * 2)]; Ech softwre component my hve its set of initiliztion routines, which my conflict on integrtion. Common initiliztion routines include interrupt initiliztion, device initiliztion, clock nd system power settings, externl memory, hep memory, nd so on. The following code listing is extrcted from the sys_init() function of the defult VisulDSP++ LwIP project. /* initilize the interrupt mnger */ di_int_init(intmgr_storge, sizeof(intmgr_storge), &response_count, &criticl_reg); /* initilize the device mnger */ di_dev_init(devmgr_storge, sizeof(devmgr_storge), &response_count, &devmgr_hndle, &imsk_storge); 4.2 Hrdwre Guidelines A problem tht often prevents functionl stndlone system from working with other components is the limited bndwidth vilble on n embedded pltform. Blckfin processors include internl buses tht hve different widths (ADSP-BF53x processors re 16 bits wide, nd the ADSP-BF561 processor is 32 bits wide). Ech bus cn run t mximum speed of 133 MHz, which implies mximum dt rte of 266 or 532 Mbyte/s, depending on the size of the internl bus. Severl fctors cn lower the mximum vilble bndwidth, such s system bus red/write turnround times, bnk conflicts, ltency due to rbitrtion logic, core nd DMA conflicts, nd so on. These fctors re ppliction-specific nd depend on the run-time interction of peripherl dt movement nd core ccesses. Section 5 discusses optimiztion techniques tht help to minimize the fctors ffecting the system bndwidth, which result in more effective use of the system resources. Building Complex VDK/LwIP Applictions Using Blckfin Processors (EE-312) Pge 5 of 12

6 4.2.1 Mnging Interrupts Severl peripherls my be mpped to single IVG level, nd severl softwre components my use the sme IVG level. Upon integrtion, the interrupt service routine from only one of the softwre component will be registered in the event vector tble (EVT). In other words, only one interrupt service routine cn be ssigned to n IVG level. Also, identifying the peripherl priorities nd mpping them to different IVG levels gretly reduces the complexity of the system Code/Dt Memory Mpping Any memory-mpping optimiztions (for exmple, mpping criticl or most executed code/dt sections to L1 memory) would need to be re-nlyzed when integrting softwre components. This is often ignored when softwre components re tken from different vendors tht hve individully hnd-optimized the memory mp for their softwre component. The behvior of the ppliction (such s the execution percentge of certin code/dt sections) my chnge in the integrted ppliction, eventully resulting in higher memory ccess ltencies compred to the individul execution of the softwre components. Code/dt mppings should therefore be re-nlyzed in the integrted ppliction Exception nd Hrdwre Error Hndlers VDK uses service exceptions to mnge tsk scheduling nd other kernel ctivities. It mps the exception hndler to routine in the kernel code. It psses ll the error exceptions to user exception routine, which it cretes by defult. For ppliction tht only use the system services librries, you hve to mp the exception hndler. However, when integrting system services ppliction into VDK project, the exception hndler should not be seprtely mpped nd ll exceptions should be hndled in the defult user exception routine creted within VDK-enbled project. Figure 3 shows the defult exception hndler routine creted by VDK project. /* UserExceptionHndler */ /* User Exception Hndler entry point */.GLOBAL UserExceptionHndler; UserExceptionHndler: /** * Hndle the exception... * * Remember tht the VDK reserves the user exception 0, which * is ccessed with the following instruction: * * EXCPT 0; * * Any other exception (user or system), is your responsibility to * hndle here. */ RTX;.UserExceptionHndler.end: Figure 3. Defult exception hndler routine creted by VDK-enbled project Error Interrupts Most peripherl error interrupts re mpped to IVG7. Therefore, it is essentil to explicitly resolve the vrious DMA or peripherl error to debug the ppliction efficiently. Using the error interrupts in your system is the best wy to determine when peripherl hs n overrun or n underrun. For exmple, higher priority resource my prevent lower priority resource from ccessing memory, which my contin dt or even DMA descriptor. Building Complex VDK/LwIP Applictions Using Blckfin Processors (EE-312) Pge 6 of 12

7 5 System Optimiztions This section presents severl hrdwre nd softwre optimiztion techniques tht will help you to fully tke dvntge of the Blckfin rchitecture. Users who re well versed with the Blckfin pltform nd the VisulDSP++ debugging environment cn skip to Section Hrdwre Considertions Although, severl system optimiztion techniques cn be incorported, the following re the recommended minimum: 16/32-bit trnsfers: Use mximum bus width for ll peripherl DMA nd memory DMA trnsfers. Initite 16-bit trnsfers for ADSP-BF53x processors, nd initite 32-bit trnsfers the ADSP-BF561 processor. Efficient use of DMA chnnels: Do not crry out two simultneous memory trnsfers on the sme DMA chnnel. SDRAM bnk prtitioning: Prtition the SDRAM into four bnks to ensure simultneous ccess to multiple dt buffers nd to minimize turn-round times. For exmple, the ADSP-BF561 EZ-KIT Lite bord hs 64 Mbytes of SDRAM, which cn be configured s four 16-Mbyte internl SDRAM bnks. To tke dvntge of the bnk structure, do not mp two dt buffers, which re ccessed simultneously, to the sme SDRAM bnk. DMA trffic control: Use DMA trffic control registers for efficient system bndwidth utiliztion. The trffic control registers provide wy to influence how often the trnsfer direction on the dt buses my chnge, by utomticlly grouping sme-direction trnsfers. Refer to [2], [3], or [4] for detils on DMA performnce optimiztion. Minimize DMA/Core conflict: Minimize core nd DMA conflicts. Avoid core ccess to externl memory. By defult, core hs higher priority over DMA for externl memory ccesses, but this cn be chnged by setting the CDPRIO bit in the EBIU_AMGCTL register. By giving DMA higher priority thn core, incoming nd outgoing dt trffic from the peripherl devices is not hlted on core ccess to the externl memory. Instruction nd dt cching: Enbling instruction nd dt cches cn drsticlly increse ppliction performnce. If the ppliction size is huge, which is usully the cse with LwIP/VDK pplictions, cche cn help to increse the performnce gretly. Refer to [4], [6], nd [8] for more detiled description of optimiztion techniques. 5.2 Softwre Considertions Executing Interrupt Service Routine Avoid dt processing in ISRs or cllbck functions. Process dt buffers in user threds. Interrupts run t higher priority thn user-defined threds. User-defined threds lwys run t IVG 15 (tht is, t the lowest priority), nd ISRs nd cllbcks [7] re executed t the corresponding IVG level. Use deferred cllbcks to lower the priority of the corresponding ISR, permitting more efficient use of CPU time. Building Complex VDK/LwIP Applictions Using Blckfin Processors (EE-312) Pge 7 of 12

8 A lower-priority ISR will hold off higher-priority ISR when the lower-priority ISR is not reentrnt. Blckfin processors provide interrupt nesting, enbling higher-priority peripherls to interrupt the execution of lower-priority interrupts Efficient buffer mngement scheme Use double-buffering scheme to void processor stlls. Double-buffering or multiple buffering ensures tht the processor cn process the current buffer while the other buffers re filled in by peripherl DMA. Figure 4 shows simple dt flow digrm for mnging dt in double-buffer implementtion. Refer to [8] where more dt flow digrms show how to mnge double/multiple dt buffers in n ppliction. Input interfce e.g. PPI, SPORT DMA Rx Line0 Rx Line1 Tx Line0 Tx Line1 DMA Output interfce Internl L1 memory receive Figure 4. Dt flow digrm for simple double-buffering scheme Compiler optimiztions Severl compiler optimiztions cn be pplied to increse the performnce. The use of the O switch nd the ip switch provide the most improvement. Using profile-guided optimiztion (PGO) lso helps to further increse the performnce. For detiled optimiztion techniques, refer to the chpter entitled Achieving Optiml Performnce from C/C++ Sources in the compiler mnul [14]. Some ISRs nd criticl computtion functions cn be hnd-optimized in ssembly to increse performnce Linker optimiztions Blckfin processor memory consists of L1 SRAM, which often is not used effectively. Mpping criticl memory nd most executed memory to L1 SRAM memories cn eliminte most of the lost cycles due to cche miss penlties. Use the sttisticl profiler (Tools -> Sttisticl profiler) to locte the most executed code nd to mp those functions in L1 SRAM memory. Also, mp criticl ISR to L1 SRAM to ensure deterministic ccess time. Refer to [9] for informtion bout code mpping on Blckfin processors. Building Complex VDK/LwIP Applictions Using Blckfin Processors (EE-312) Pge 8 of 12

9 6 Generl Debugging Tips Aprt from the usul debugging cpbilities such s brekpoints nd using the Expressions window or the Locls window, the combintion of register set on the Blckfin rchitecture nd the VisulDSP++ environment provides rich set of debugging tools tht enble you to debug complex systems. These re some of the key debug tools: 6.1 VDK History Window Use the VDK History window (Figure 5) to trck thred sttus, events, nd rce conditions between threds, nd so on. This window is prticulrly useful when you debug pplictions tht involve multiple threds. Open the VDK History window from the VisulDSP++ IDDE min menu by choosing View -> VDK windows -> History. Figure 5. VDK History window 6.2 VDK Sttus Window The VDK Sttus window (Figure 6) displys the sttus of ll threds, semphores, messges, nd so on defined within the system. The VDK Sttus window lso indictes the error code in cse of Kernel Pnic. Common mistkes tht generte kernel pnic include clling restricted VDK API functions from ISRs or cllbcks or ccessing resources of thred tht hs been destroyed. Open the VDK Sttus window from the VisulDSP++ IDDE min menu by choosing View -> VDK windows -> Sttus. Building Complex VDK/LwIP Applictions Using Blckfin Processors (EE-312) Pge 9 of 12

10 Figure 6. VDK Sttus window 6.3 Trce Unit nd Sequencer Registers To debug n exception, you must first locte the cuse of the exception by exmining the EXCAUSE field in the SEQSTAT register. The ddress of the instruction tht cused the exception is stored in RETX register. Rerun the ppliction by plcing brekpoint t the excepting ddress nd enbling the Trce Buffer Unit by setting two bits in the TBUFCTL register. Then you cn exmine the sequence of instructions from the Trce Buffer Unit to determine the exct cuse of exception. 6.4 Wtchpoint Unit The wtchpoint register provides mens of debugging situtions in which n error occurs only on the n th ccess to n instruction or dt. In such cses, n emultion event cn be generted using the wtchpoint registers the n-1 th time the instruction or dt is ccessed; then you step through to find the cuse of exception or error. 6.5 Peripherl Sttus Registers If DMA or peripherl error is detected, you cn exmine the DMA/peripherl sttus registers to locte the cuse of error. Aprt from configurtion mistkes, errors (such s DMA overrun or underrun errors) occur due to inefficient system design. At this point, it my help to mnge the dt buffers more efficiently or further divide the ppliction into smller tsks. Also, if using system service librries (SSL), most of the error codes re identified by the return codes of system services API cll nd event codes in the cllbck function. The SSL covers events cusing the DMA or peripherl errors. Refer to ny of the exmples included in the Multimedi strter kit [14]. The bove list provides n overview of some debugging methods. For more informtion, refer to [17]. Building Complex VDK/LwIP Applictions Using Blckfin Processors (EE-312) Pge 10 of 12

11 7 Conclusion Integrting severl softwre components is complex nd chllenging tsk. When you use multiple softwre components, system's complexity grows in terms of nlyzing system resource utiliztion, bndwidth requirements, resolving potentil softwre nd hrdwre conflicts, debugging the ppliction, nd so on. The guidelines in this document cn help you to void common pitflls tht my rise in integrting softwre components. The guidelines id in developing n optimized nd robust ppliction. Supported LwIP Fetures For list of current fetures vilble with LwIP concurrent with the relese of this EE-Note, refer to the ssocited.zip file. Check for fetures tht hve been dded to VisulDSP++ in the ltest relese notes, which re locted here: es/index.html Building Complex VDK/LwIP Applictions Using Blckfin Processors (EE-312) Pge 11 of 12

12 Additionl Reding [1] LwIP User Guide, <instll_pth>\anlog Devices\VisulDSP 4.5\Blckfin\lib\src\lwip\docs. [2] BF537EthernetDeviceDriverDesign.doc, <instll_pth>anlog Devices\VisulDSP 4.5\Blckfin\lib\src\lwip\docs. [3] SMSCLAN91C111_DeviceDriver.doc, <instll_pth>anlog Devices\VisulDSP 4.5\Blckfin\lib\src\lwip\docs. [4] ADSP-BF533 Blckfin Processor Hrdwre Reference. Rev 3.2, July Anlog Devices, Inc. [5] ADSP-BF561 Blckfin Processor Hrdwre Reference. Rev 1.1, Februry Anlog Devices, Inc. [6] ADSP-BF537 Blckfin Processor Hrdwre Reference. Rev 2.0, December Anlog Devices, Inc. [7] Embedded Medi Processing. Dvid Ktz nd Rick Gentile. Newnes Publishers., Burlington, MA, USA, [8] Digitl Video nd HDTV. Chrles Poynton. Morgn Kufmnn Publishers Inc., Sn Frncisco, CA, USA, [9] Video Frmework Considertions for Imge Processing on Blckfin Processors (EE-276). Rev 1, September Anlog Devices Inc. [10] VisulDSP Device Drivers nd System Services Mnul for Blckfin Processors. Rev 2.0, Mrch Anlog Devices, Inc. [11] Video Templtes for Developing Multimedi Applictions on Blckfin Processors (EE-301). Rev 1, September Anlog Devices Inc. [12] PGO-Linker- A Code Lyout Tool for the Blckfin Processors. (EE-306). Rev 1, December Anlog Devices Inc. [13] VisulDSP 4.5 Kernel (VDK) Users Guide. Rev 2.0, April Anlog Devices, Inc. [14] Multimedi Strter Kit. Anlog Devices Inc. [15] VisulDSP Linker nd Utilities Mnul, Rev 2.0, April Anlog Devices Inc. [16] VisulDSP Blckfin C/C++ Compiler nd Librry Mnul, Rev 4, April 2006, Anlog Devices Inc. [17] Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools (EE-307). Rev 1, December 2006, Anlog Devices Inc. References [18] Unix Network Progrmming, volumes 1-2. W. Richrd Stevens, Prentice Hll, USA, [19] MicroC/OS-II. Jen J. Lbrosse. CMP Books, Sn Frncisco, CA, USA, [20] Computer Networks, Andrew Tnenbum, Prentice Hll, USA, [21] Associted ZIP File. Rev 1, Mrch Anlog Devices, Inc. Document History Revision Rev 1 Mrch 2, 2007 by Kushl Snghi Description Initil Relese. Building Complex VDK/LwIP Applictions Using Blckfin Processors (EE-312) Pge 12 of 12