Engineer-to-Engineer Note

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1 Engineer-to-Engineer Note EE-232 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our on-line resources nd Configuring the Signl Routing Unit of ADSP-2126x SHARC DSPs Contributed by K. Mlsky Rev 1 Februry 12, 2004 Introduction The ADSP-2126x fmily of SHARC DSPs is cpble of interfcing with wide vriety of peripherls. Much of this verstility comes from the processor s soft connections between the I/O ports nd the physicl pckge pins. When most processors re designed into rel-world systems, mny device pins re tied high or low, pulled up, pulled down, or left unconnected. A complex system often hs mny input pins with fixed or defult vlues tht must be hrd-wired nd unused outputs pins. The Signl Routing Unit (SRU) on n ADSP-2126x DSP is softwre-controlled mtrix tht cn eliminte the need for pins tht do not serve ny true I/O purpose. The SRU provides mximum flexibility by llowing you to define the function of the 20 pins of the digitl udio interfce (DAI). However, this flexibility brings complexity tht cn be overwhelming when beginning new design. This document provides guidnce for engineers who re strting their first project using the SRU nd the DAI pins. It offers helpful hints nd tricks tht my ssist experienced users. Getting Strted The SRU, which is documented in the ADSP- 2126x SHARC DSP Peripherls Mnul [1], cn be somewht difficult to pproch. By its nture, ny connection mtrix requires cler understnding of wht is being connected. The nming convention for these endpoints is very consistent, but frequently counterintuitive. In n ttempt to mke the nomenclture more intuitive, we ll begin by using fmilir terms nd focusing on the outside of the processor. Step 1: Tke Inventory of the Unique Signls As mentioned bove, only signls tht ctully provide informtion to nd from peripherls need to be connected to the SHARC DSP. Since there is mens of routing within the DSP, signls need only to be connected to single pin, regrdless of the number of internl plces the signl is used. You do not hve to connect the sme signl to two or more DAI externl pins. Identify the peripherls tht you re trying to connect to the SHARC DSP, nd count the unique signls. If the sme clock or frme sync is connected to multiple devices, it counts s one signl. When seril dt strem drives multiple output devices, it lso counts s single signl. List the unique I/O signls nd look crefully to see wht else you my be ble to eliminte. For exmple, if you find two signls re identicl, but of opposite polrity (inverted), count them s one signl, s the SRU cn generte either from the other. If clock signl is phse-ligned, integer sub-multiple of nother clock signl, group them together. The Precision Clock Genertor (PCG) is peripherl within the DAI tht my llow you to connect only the fstest clock. For exmple, if there is clock t frequency f nd nother t f/8, it is likely tht only the fster clock needs DAI pin. Red Copyright 2004, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices Applictions nd Development Tools Engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 bout the PCG in the ADSP-2126x SHARC DSP Peripherls Mnul [1] for detils. Step 2: Note the Direction of Signl Flow Next to ech signl in your list, indicte whether it should be n input to the pin buffer, n output from the pin buffer, or bidirectionl.! The externl connection to the SHARC DSP DAI pins (the wire led or bll) is prt of peripherl known s pin buffer. Pin buffers will be explined in detil in the next section. For now, just think of them s I/O pins on the SHARC with progrmmble behvior. Most pin buffers re used only in one direction in given design. Note tht mny peripherls hve pins tht re cpble of being bidirectionl, but re only used in one direction in the system. When pin buffer is unidirectionl, progrmming the SRU is drmticlly simplified. In cses where the pin is bidirectionl, determine wht cuses the direction to chnge. Is it the stte of nother pin? Is it the stte of processor-level control register? Is it the softwre configurtion of port? Think bout wht my be controlling when the SHARC is driving logic vlue onto the bidirectionl pin nd when the pin is just reding logic input. Step 3: Allocte the DAI Pins At this point, it is likely tht you will hve reduced your list to 20 or fewer signls. If you hve few extr, don t pnic. There re dditionl pins tht my be designted s vrious types of GPIO, including FLAGS, IRQ, nd device selects. Build chet sheet tht lists the DAI pin numbers (1-20), the signl to which you re connecting ech pin, nd whether it is n output, input, or bi-directionl (from the perspective of the SHARC DSP). Even if the schemtics re esy to red, clen version of this tble will be invluble until your system is up nd running. Once the SRU is configured correctly (one or more routing ptterns depending on your ppliction), most of this will become trnsprent. Progrmming the SRU Think of ech physicl DAI s 3-terminl peripherl with logicl connections for n input, n output, nd n enble tht ctivtes the pin buffer mplifier. Interfce to SRU PBxx_O PBxx_I PBENxx_I IN Figure 1. A Pin Buffer PIN BUFFER ENABLE OUT PBxx_O Externl Pckge Connection Pin A pin buffer is like smll buffer mplifier tht cn source enough current to drive the pin nd trce on the circuit bord. When switched on (i.e., when its enble input is logic high), the logic vlue t the pin buffer input is driven onto the pin buffer output. When switched off (i.e., when its enble input is logic low), the buffer mplifier is high impednce, nd the logic level of the pin buffer output is esily controlled by n externl source. Pin buffers re the logicl gtewy for the physicl IC pckge leds ssocited with the DAI. Step 4: Progrm the Inputs to the SHARC DSP Understnding the nomenclture is, rgubly, the most difficult prt of using the SRU. Progrmming is very simple. Ensure tht you understnd the next prgrph before continuing. Since pin buffer is n on-chip peripherl, the signl you connect to the physicl pckge is Configuring the Signl Routing Unit of ADSP-2126x SHARC DSPs (EE-232) Pge 2 of 6

3 referred to s the pin buffer output. Although it is n input to the SHARC, it is n output from the pin buffer. Note tht Figure 1 shows two connections to the trce, which re lbeled PBxx_O (pin buffer output). One of them is prt of the SRU interfce, nd the other is the externl pckge connection pin. When the pin buffer is used s n input, the signl follows this pth. Stted nother wy, pin buffer output within the SRU is lwys equl to the logic vlue on the externl pin. All DAI pins tht do not chnge signl flow direction cn be routed in the SRU reltively simply. The signl follows the hrd-wired pth mentioned bove. For ech DAI pin tht is n input to the SHARC DSP, tie the pin buffer enble low to ensure tht the pin does not drive the line. Next, connect the pin buffer output to the plce in the SRU where you wnt to connect the signl. For exmple, the following mcro instructions connect DAI pin 7 to the frme sync input of SPORT4: SRU(LOW,PBEN07_I); SRU(DAI_P07_O,SPORT4_FS_I); Listing 1. Configuring DAI Pin s n Input Bit fields in SRU registers re lwys inputs nd therefore cn hve one vlue only. The nme of the node ends in _I to remind you tht it is n input. Only one output my be connected to ech input. The destintion shown bove my be ny input shown in the bitfields of the SRU registers for Group A through Group D. For exmple, n externl frme sync is connected to SPORT3 s follows: SRU(LOW,PBEN07_I); SRU(DAI_P07_O,SPORT3_FS_I); Listing 2. DAI Pin Input to SPORT3 Frme Sync An output signl is just n encoding n enumerted vlue entered into bit field. Thus, n output my connect to ny number of inputs within the sme group. The third SRU connection is not lwys necessry, but it is recommended tht you tie the pin buffer input to low s follows: SRU(LOW,DAI_P07_I); Listing 3. Setting n Unused Pin Buffer Input Low There re couple of resons for this. First, it cn mke your code clerer. If the enble nd input of pin buffer re tied low, tht DAI pin is obviously being used s n input (or not t ll). Also, preventing logic from unnecessry switching sves power nd reduces RF rdition. For exmple, there is no reson to pss high frequency clock through the SRU if it will be ignored. Lst, ll of the DAI pins re connected to the seril ports when the processor comes out of reset. The defult vlue is not logic low. If there is mistke in your code tht enbles the pin buffer, the output my be driven with signl tht is difficult to identify. Agin, this is not strictly necessry, but it is recommended prctice. Step 5: Progrm the Outputs from the SHARC For ech pin tht is n output from the SHARC DSP, tie the pin buffer enble high. This ensures tht the pin buffer does drive signl onto the externl pin. More specificlly, it ensures tht the logic vlue t the pin buffer s input is driven onto the pin buffer s output. Connect the (internl) source signl to the pin buffer input. For exmple, use the following mcro instructions to connect the output of Timer 0 to DAI pin 14: SRU(HIGH,PBEN14_I); SRU(TIMER0_O,DAI_P14_I); Listing 4. Configuring DAI Pin s n Output Note tht the source signl (TIMER0_O in this exmple) must be n output listed in the Group D Sources Pin Signl Assignments tble in the Configuring the Signl Routing Unit of ADSP-2126x SHARC DSPs (EE-232) Pge 3 of 6

4 ADSP-2126x SHARC DSP Peripherls Mnul [1], nd will end in _O s reminder tht it is n output.! An input my be connected to only one output, but n output my be connected to multiple inputs. An output signl my be connected to numerous inputs. For exmple, connect the clock output of SPORT2 to both DAI pin 7 nd s clock input for SPORT1 s follows: /* Mke DAI pin 14 n output */ SRU(HIGH,PBEN14_I); /* Send the clock out DAI pin 14 */ SRU(SPORT2_CLK_O,DAI_P14_I); /* Use the SPORT1 clock for SPORT2 */ SRU(SPORT2_CLK_O,SPORT1_CLK_I); Listing 5. Routing n Output to More thn One Input In Listing 5, insted of connecting clock output to pin buffer input nd then pin buffer output to the other SPORT clock input, notice tht both of the inputs re connected directly to the clock output. This is becuse the input nd the output of the pin buffer re not gurnteed to hve the sme vlue. As long s the pin buffer enble, PINEN14, is set to high (sserted), this disychining is equivlent to the prllel connection mde bove. However, if the pin enble is desserted, the pin cts s n input nd the clock input to SPORT1 is driven from off-chip. Unless you specificlly wnt the connection to chnge bsed on the vlue of the pin buffer enble, the best prctice is to connect directly to the source s shown in Listing 5.! It is not necessry to route pin buffer output when it is not needed. Step 6: Progrm the Bi-directionl DAI Pins As mentioned in Step 2, pin tht serves s both n input nd n output must hve signl present in the SRU tht dicttes the flow direction. Severl peripherls, which re explicitly designed to be bidirectionl, hve input, output, nd enble nodes ssocited with single signl. For exmple, ech of the seril port signls (clock, frme sync, dt chnnel A, nd dt chnnel B) cn be n input or n output. The direction of these signls is controlled in the core by writing to the SPCTLx registers. You cn connect the clock signl for SPORT0 to DAI pin 6 s follows: SRU(DAI_P06_O,SPORT0_CLK_I); SRU(SPORT0_CLK_O,DAI_P07_I); SRU(SPORT0_CLK_PBEN_O,PBEN07_I); Listing 6. A Bidirectionl DAI Pin Refer to the discussion of bidirectionl pins in the ADSP-2126x SHARC DSP Peripherls Mnul [1] for more informtion. Also, the tble of vlid sources for group F, locted in the mnul's ppendix, describes the I/O register nd includes ll pin enble signls from ll explicitly bidirectionl peripherls. Step 7: Be Cretive nd Use of the Options Any Group F source cn control pin direction, nd you cn perform tricks by tking dvntge of the MISC signls. You re not limited to using these internlly generted enble signls. The code in Listing 7 my be little hrd to follow t first, but it demonstrtes very powerful functionlity. SPORT1 is lwys clock mster nd SPORT0 is lwys clock slve. Furthermore, the clock output from SPORT1 is lwys being driven s n output on DAI pin 4. The clock input to SPORT0 is lwys the sme s the externl signl on DAI pin 7. DAI pin 1 is lwys n input for control signl. /* SPORT1 clock is n output */ SRU(SPORT1_CLK_O,DAI_P04_I); SRU(HIGH,PBEN04_I); /* Pin 7 direction is set by pin 1 */ SRU(MISCA0_O,PBEN07_I); SRU(DAI_PIN01_O,MISCA0_I); Configuring the Signl Routing Unit of ADSP-2126x SHARC DSPs (EE-232) Pge 4 of 6

5 /* When pin 7 is n input, the offchip signl drives SPORT0 clock */ SRU(DAI_P07_O,SPORT0_CLK_I); /* When pin 7 is n output, SPORT1 clock drives SPORT0 clock */ SRU(SPORT1_CLK_O,DAI_P07_I); /* Pin 1 (dir control) is n input */ SRU(LOW,PBEN01_I); SRU(LOW,DAI_P01_I); Listing 7. DAI Pin Output The tricky prt is tht DAI pin 7 (SPORT0 clock in) is bidirectionl pin, nd its direction is controlled by DAI pin 1. When DAI pin 1 is low, DAI pin 7 is n input nd SPORT0 receives its clock signl from off-chip. When DAI pin1 is high, DAI pin 7 is n output (equl to the SPORT1 clock output) nd SPORT0 receives the internlly generted clock from SPORT1. Step 8: Optimize the Initiliztion Code Ech mcro commnd used in this document expnds to six SHARC DSP ssembly lnguge instructions. However, ech mcro cll modifies smll bit field of one SRU control register only. In SHARC ssembly, register cn be loded with full 32-bit vlue in single instruction. In typicl system, the SRU is primrily configured t initiliztion, nd modified infrequently. Write nd debug your ppliction using the mcro s shown bove. Crete subroutine tht encpsultes lrge number of these mcro clls. When you feel tht the routing is correct nd your I/O is working smoothly, strt your ppliction in the debugger nd plce brekpoint just fter you hve completely configured the SRU. Open the debug windows tht show the vlues of the vrious SRU registers nd note their vlues. You cn now comment out ll of the mcro clls (leve them in plce s documenttion), nd replce them with smll number of instructions tht write the vlue of the SRU control register completely. For exmple, the following mcro clls connect the frme syncs inputs for ll six SPORTs to DAI pin 3: SRU(DAI_P03_O,SPORT0_FS_I); SRU(DAI_P03_O,SPORT1_FS_I); SRU(DAI_P03_O,SPORT2_FS_I); SRU(DAI_P03_O,SPORT3_FS_I); SRU(DAI_P03_O,SPORT4_FS_I); SRU(DAI_P03_O,SPORT5_FS_I); Listing 8. Configuring Frme Syncs Using Mcros This will expnd to 36 instructions, which will set the vlue of the control register SRU_FS0. The following in-line ssembly instruction performs the sme function: sm( r0=0x ; dm(sru_fs0)=r0; ); Listing 9. Configuring Frme Syncs Using Inline sm This reduces the initiliztion code size from 36 instructions to 2 nd removes the overhed penlty ssocited with the mcro. You do not hve to clculte this vlue (or wste time debugging it) becuse it displys directly in the debugger window. Obviously, if you re writing in ssembly, you cn ignore the wrpper. For typicl system, you cn sve the code spce nd execution time of few hundred 48-bit instructions. Summry The ggregte bndwidth of the DAI pins is much higher thn it my pper t first glnce becuse the SRU elimintes unnecessry pins. An even less obvious benefit, however, is the myrid wys in which one signl cn be used to mnipulte nother signl, such s gting, triggering, msking, nd re-clocking. This ppliction note scrtches the surfce in describing the possibilities. DAI resources, such s the Precision Clock Genertors, verstile timers, flgs, interrupt sources, nd pin buffer Configuring the Signl Routing Unit of ADSP-2126x SHARC DSPs (EE-232) Pge 5 of 6

6 inverters increse the number of trick permuttions drmticlly. Be cretive, nd you my be surprised t wht the SRU hs to offer. References [1] ADSP-2126x SHARC DSP Peripherls Mnul. Revision 1.0, December Anlog Devices, Inc. Document History Version Rev 1 Februry 12, 2004 by K. Mlsky Description Initil Relese Configuring the Signl Routing Unit of ADSP-2126x SHARC DSPs (EE-232) Pge 6 of 6