PCI-4SIP. Slave Quad IndustryPack Carrier for PCI systems REFERENCE MANUAL Version 1.2 September 2001
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1 PCI-4SIP Slave Quad IndustryPack Carrier for PCI systems REFERENCE MANUAL Version 1.2 September 2001 ALPHI TECHNOLOGY CORPORATION 6202 S. Maple Avenue #120 Tempe, AZ USA Tel: (480) Fax: (480)
2 NOTICE The information in this document has been carefully checked and is believed to be entirely reliable. While all reasonable efforts to ensure accuracy have been taken in the preparation of this manual, ALPHI TECHNOLOGY assumes no responsibility resulting from omissions or errors in this manual, or from the use of information contain herein. ALPHI TECHNOLOGY reserves the right to make any changes, without notice, to this or any of ALPHI TECHNOLOGY s products to improve reliability, performance, function or design. ALPHI TECHNOLOGY does not assume any liability arising out of the application or use of any product or circuit described herein; nor does ALPHI TECHNOLOGY convey any license under its patent rights or the rights of others. ALPHI TECHNOLOGY CORPORATION All Rights Reserved This document shall not be duplicated, nor its contents used for any purpose, unless express permission has been granted in advance. ALPHI TECHNOLOGY CORP. Page ii REV 1.2
3 TABLE OF CONTENTS 1. GENERAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION REFERENCE MATERIALS LIST 3 2. HOST (PCI) SIDE PCI CONFIGURATION REGISTERS PCI BASE ADDRESS REGISTERS PCI IP STATUS REGISTER PCI OPERATION REGISTERS IP ID AND I/O REGION IP MEMORY REGION 8 3. IP DETAILS IP MODULE ID SPACE IP MODULE IO SPACE IP MODULE MEMORY SPACE IP MODULE INTERRUPT SPACE RESET SIGNALS JUMPER DESCRIPTIONS LED INDICATORS CONNECTIONS IP I/O CONNECTORS (P1, P2, P4, P5) 12 Table 2.1: CPCI Configuration Registers 4 Table 5.1 Jumper Descriptions 9 Table 6.1 LED Descriptions 10 Table 7.1: I/O Connector Model Numbers 11 ALPHI TECHNOLOGY CORP. Page iii REV 1.2
4 1. GENERAL DESCRIPTION 1.1 INTRODUCTION The PCI-4SIP is a PCI bus IP carrier. The PCI-4SIP provides mechanical support and the electrical interfaces of four single width IP modules. Multiple PCI-4SIP boards may be installed in a single desktop system. The primary features of the PCI-4SIP are as follows: Support for up to four IP modules 8 MHz or 32 MHz IP operation via jumper selection Direct I/O or Memory mapped access from PCI bus via AMCC 5933 PCI Chip Full interrupt support of host Front panel I/O connectors for all IP s 1.2 FUNCTIONAL DESCRIPTION A functional block diagram of the PCI-4SIP is presented below in Figure 1-1. The jumper placement and the connector placement are depicted in Figure 1-2. The PCI-4SIP operates as a slave that is managed by the host processor on the PCI bus. Each pair of IP modules share a common clock that can be jumpered for 8 or 32 MHz operation. The PCI-4SIP is supported by ALPHI Technology under Windows NT by a Board Support Package, which is supplied with the card. Other documentation supplied with the card will describe this support in full detail. PCI Bus IP A Connector PCI to Local Bus Bridge Mailbox Registers IP B IP C IP D Connector Connector Connector Figure 1.1: Block Diagram ALPHI TECHNOLOGY CORP. Page 1 REV 1.2
5 P 4 L1 L2 L3 IP IP A W2W3 W4W5 W6W W1 1 2 W8 IP D P L4 P 5 L5 IP A IP B IP C 10 L6 Figure 1.2: Jumper and Connector Locations ALPHI TECHNOLOGY CORP. Page 2 REV 1.2
6 1.3 REFERENCE MATERIALS LIST The reader should refer to the PCI Local Bus Specification for a detailed explanation of the PCI bus architecture and timing requirements. This specification is available from the following source: PCI Special Interest Group PO Box Portland, OR Tel: (800) Tel: (503) Fax: (503) The reader is also referred to the S5933 PCI Controller data book: AMCC Applied Micro Circuits Corporation 6195 Lusk Boulevard San Diego, CA Tel: (800) WindowsNT and Windows95 Programming Tools: BlueWater Systems 144 Railroad Ave. Suite #217 Edmonds, WA Tel: (206) Fax: (206) info@bluewatersystems.com Web: ALPHI TECHNOLOGY CORP. Page 3 REV 1.2
7 2. HOST (PCI) SIDE 2.1 PCI CONFIGURATION REGISTERS The card presents the following configuration values to the CPCI system, based on the values stored in the NVRAM device read by the AMCC PCI interface chip. Register Vendor ID Device ID Revision ID Class Code Interrupt Line Interrupt Pin Multifunction Device Build In Self Test Latency Timer Minimum Grant Maximum Latency Expansion ROM Size Value (Meaning) 0x13c5 (ALPHI Technology) 0x0402 (PCI-4SIP) 0x00 0xff0000 (Device does not fit into defined class codes) 0xff A No No 0x00 0x00 0x00 None Table 2.1: CPCI Configuration Registers 2.2 PCI BASE ADDRESS REGISTERS The card requests base address regions from the PCI system after RESET, based on the values stored in the NVRAM device read by the AMCC PCI interface chip. The decode addresses of these regions are assigned by the host processor. The PCI-4SIP uses 3 of the 4 AMCC mapped base address registers. The AMCC is normally programmed at the factory to request the following resource from the PCI BIOS: BASE BAR From To Description Type 0 0x x F AMCC PCI Operation Registers MEM 1 0x x000007FF IP ID and IO Region MEM 3 0x x01FFFFFF IP Memory Region (A & B) MEM 4 0x x01FFFFFF IP Memory Region (C & D) MEM Table 2.2: Base Address and Use NOTE: The AMCC has been programmed to request memory above 1 Mbytes. ALPHI TECHNOLOGY CORP. Page 4 REV 1.2
8 2.3 PCI IP STATUS REGISTER This register is available to give status of DMA requests and Interrupt requests of each of the four IP locations. To access these registers make a read at base address of IP-A and add C0. With no IP s installed you should see $FFFF. The following Table 2.3 will read results. Bit Register Name Bit 0 INTREQA0 Bit 1 INTREQA1 Bit 2 INTREQB0 Bit 3 INTREQB1 Bit 4 INTREQC0 Bit 5 INTREQC1 Bit 6 INTREQD0 Bit 7 INTREQD1 Bit 8 DMARQA0 Bit 9 DMARQA1 Bit 10 DMARQB0 Bit 11 DMARQB1 Bit 12 DMARQC0 Bit 13 DMARQC1 Bit 14 DMARQD0 Bit 15 DMARQD1 Table 2.3: PCI IP STATUS REGISTER ALPHI TECHNOLOGY CORP. Page 5 REV 1.2
9 2.4 PCI OPERATION REGISTERS PCI-4SIP REFERANCE MANUAL The host processor communicates with the PCI-4SIP card via the AMCC pass-through interface. After the base address register has been programmed by the PCI configurator, incoming PCI I/O or Memory cycles are used to access the registers of the AMCC chip. The PCI Operation Registers of the AMCC 5933 chip are depicted below: Offset Register Name 0x00 OMB1 Outgoing Mailbox Register 1 0x04 OMB2 Outgoing Mailbox Register 2 0x08 OMB3 Outgoing Mailbox Register 3 0x0C OMB4 Outgoing Mailbox Register 4 0x10 IMB1 Incoming Mailbox Register 1 0x14 IMB2 Incoming Mailbox Register 2 0x18 IMB3 Incoming Mailbox Register 3 0x1C IMB4 Incoming Mailbox Register 4 0x20 FIFO Register Port (bi-directional) 0x24 MWAR Master Write Address Register 0x28 MWTC Master Write Transfer Counter 0x2C MRAR Master Read Address Register 0x30 MRTC Master Read Transfer Counter 0x34 MBEF Mailbox Empty/Full Status 0x38 INTCSR Interrupt Control/Status Register 0x3C MCSR Bus Master Control/Status Register Table 2.4: AMCC Registers (HOST) For more information about these registers refer to the AMCC PCI controller manual. ALPHI TECHNOLOGY CORP. Page 6 REV 1.2
10 2.5 IP ID AND I/O REGION PCI-4SIP REFERANCE MANUAL 16 bit accesses to the following offsets from BAR1 will allow for communication with the four IPs. Unspecified addresses are reserved. Note that the PCI-4SIP only supports 16-bit access to the I/O regions, but it does support 32-bit access to memory regions. FROM TO R/W REGION 0x00 0x3F R/W IP_A ID Space 0x80 0x81 R IP_A Interrupt Vector 0 0x82 0x83 R IP_A Interrupt Vector 1 0x100 0x17F R/W IP_A I/O Space 0x200 0x23F R/W IP_B ID Space 0x280 0x281 R IP_B Interrupt Vector 0 0x282 0x283 R IP_B Interrupt Vector 1 0x300 0x37F R/W IP_B I/O Space 0x400 0x43F R/W IP_C ID Space 0x480 0x481 R/W IP_C Interrupt Vector 0 0x482 0x483 R/W IP_C Interrupt Vector 1 0x500 0x57F R/W IP_C I/O Space 0x600 0x63F R/W IP_D ID Space 0x680 0x681 R/W IP_D Interrupt Vector 0 0x682 0x683 R/W IP_D Interrupt Vector 1 0x700 0x77F R/W IP_D I/O Space 0xC0 R Interrupt Pending 0xC1 Bit 0 Bit 1 Bit 2 Bit 3 R/W Read Error IP A IP B IP C IP D Table 2.5: IP ID and I/O Regions Note: Read error To clear an error, you must write a 1 to the corresponding Bit. Example: If IP A has an error 0xC1 Read Bit 0=1 Error IP A 0xC1 Write Bit 0=1 Error IP A Clear ALPHI TECHNOLOGY CORP. Page 7 REV 1.2
11 2.6 IP MEMORY REGION 16 bit and 32 bit accesses to the following offsets from BAR3 & BAR4 will allow for communication with the four IPs. If the jumper is set for 32-bit access, then all four IPs are strobed. AMCC FROM TO R/W REGION BAR3 0x x7FFFFF R/W IP_A Memory Space BAR3 0x xFFFFFF R/W IP_B Memory Space BAR4 0x x7FFFFF R/W IP_C Memory Space BAR4 0x xFFFFFF R/W IP_D Memory Space Table 2.6: IP Memory Regions 3. IP DETAILS Please consult the IP User s Manual for details about accessing the particular IP used. ALPHI TECHNOLOGY CORP. Page 8 REV 1.2
12 3.1 IP MODULE ID SPACE Each IP must support identification PROM. The PCI-4SIP decodes 64 bytes of ID space for each IP module. The ID PROM contains information about each IP, which is defined in the Industry Pack Specification. The four IP ID s spaces can be accessed at fixed offsets from Base Address 1, as indicated in Table 2.5. The information required for the most common IP PROM format is shown below: 3.2 IP MODULE IO SPACE OFFSET DESCRIPTION VALUE 0x00 ASCII I 0x49 0x02 ASCII P 0x50 0x04 ASCII A 0x41 0x06 ASCII C 0x43 0x08 Manufacturer ID 0x0A Model No 0x0C Revision 0x0E Reserved 0x00 0x10 Driver ID, Low Byte 0x12 Driver ID, High Byte 0x14 Number of bytes used 0x0C 0x16 CRC OFFSET DESCRIPTION VALUE 0x18-0x3F User Space Table 3.1: Typical ID Space Layout The PCI-4SIP decodes 128 bytes of IO space for each IP module. The four IP I/O spaces can be accessed at fixed offsets from Base Address 1, as indicated in Table IP MODULE MEMORY SPACE The PCI-4SIP decodes 8 Mbytes of MEM space for each IP module. The four IP MEM spaces can be accessed at fixed offsets from Base Address 2 and Base Address 3, indicated in Table 2.6. ALPHI TECHNOLOGY CORP. Page 9 REV 1.2
13 3.4 IP MODULE INTERRUPT SPACE The PCI-4SIP routes the interrupts from all IP modules to the INTA# signal on the PCI bus. The PCI-4SIP decodes 2-16-bit words of INT space for each IP module to supply an optional interrupt vector. The four IP INT spaces can be accessed at fixed offsets from Base Address 1, as indicated in Table 2.5. IMB4 in the AMCC 5933 PCI Interface chip is written by the PCI-4SIP hardware when one or more IP modules are asserting an interrupt. If incoming Mailbox 4 Byte 3 interrupts have been enabled, then the PCI-4SIP will assert INTA#. Some IP modules may require that the host processor perform a read to INT space to clear pending interrupts. The PCI Operation Registers MBEF and INTCSR can be used to manage IP interrupts. See the Board Support Package for examples of how to support HOST interrupts. 4. RESET SIGNALS The PCI-4SIP can be reset from two different sources: At power on or when the PCI RESET is asserted, the watchdog timer will hold the IP reset lines low for 200 ms. The AMCC has a bit called SYSRST that the HOST can toggle to reset the IP's. Software should hold the RESET asserted for 200 ms to meet the IP specifications. 5. JUMPER DESCRIPTIONS JUMPER FACTORY SETTING DESCRIPTION W1 1 & 2 A & B 16bit enable W1 3 & 4 C & D 16bit enable W2 None IP_A IPSTROBE 1 & 2 Strobe In - 2 & 3 Strobe Out W3 None IP_B IPSTROBE 1 & 2 Strobe In - 2 & 3 Strobe Out W4 None IP_C IPSTROBE 1 & 2 Strobe In - 2 & 3 Strobe Out W5 None IP_D IPSTROBE 1 & 2 Strobe In - 2 & 3 Strobe Out W6 2 & 3 IPCLK-AB ( 8Mhz Factory ) 1 & 2 ( 32 MHz ) W7 2 & 3 IPCLK-CD ( 8Mhz Factory ) 1 & 2 ( 32 MHz ) W8 None External Strobe Input W9 None PCI Reset Note: Table 5.1 Jumper Descriptions 1- W1 jumper is used to configure the board to access 16/32 Bit IP Modules. Standard IP are 16 Bits modules. 2- W2-5 jumpers are used to Synchronize multiple IP depending if the IP module is capable to generate or receive a signal. 3- W6,7 jumpers are used to select the IP module clocks, 8/32MHZ 4- W8 jumper is used to supply an External Signal to generate an IP strobe. ALPHI TECHNOLOGY CORP. Page 10 REV 1.2
14 5- W9 jumper is used to reset the carrier board. ALPHI TECHNOLOGY CORP. Page 11 REV 1.2
15 6. LED INDICATORS There are Six LED indicators visible at the PCI card bracket. They are they are labeled on the PCB as L1 L6 where L1 is at the top of the card. The LED s have the following meanings: 7. CONNECTIONS LED LEGEND Meaning L1 IP-D HOST is accessing IP-D. L2 IP-C HOST is accessing IP-C. L3 PCI-WR HOST is writing to PCI4SIP. L4 PCI-RD HOST is reading from PCI4SIP. L5 IP-B HOST is accessing IP-B. L6 IP-A HOST is accessing IP-A. 7.1 IP I/O CONNECTORS (P1, P2, P4, P5) Table 6.1 LED Descriptions Connector I/O for P2 IP_A P3 IP_B P8 IP_C P9 IP_D 50 pin Hi-ROSE connectors are used to route all of the IP I/O signals off the card. ALPHI Technology can supply transition modules and cable assemblies to meet any special requirements. Contact the factory for additional information. Connectors are manufactured by HiROSE they can be found at Use On PC Board Model HI-F6A-50PA-1.27DS Table 7.1: I/O Connector Model Numbers Pin 25 Pin 1 Pin 50 Pin 26 Figure 7.1: IP I/O CONNECTORS The I/O signals for the four IP s are directly routed off the card through the front panel. ALPHI TECHNOLOGY CORP. Page 12 REV 1.2
16 ALPHI TECHNOLOGY CORP. Page 13 REV 1.2
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