Automotive DDR3L-RS SDRAM

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1 Automotive DDR3L-RS SDRAM MT4KG4 28 Meg x 4 x 8 banks MT4K52M8 64 Meg x 8 x 8 banks MT4K256M6 32 Meg x 6 x 8 banks 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Description Description The.35R3L-RS SDRAM device is a low-current self refresh version of the.35r3l SDRAM device via the TCSR feature. Unless stated otherwise, the DDR3L-RS SDRAM device meets the functional and timing specifications listed in the equivalent density standard or automotive DDR3L SDRAM data sheet located on Features = Q =.35V V Backward-compatible to = Q =.5V ±.75V Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs CK, CK# 8 internal banks Nominal and dynamic on-die termination ODT for data, strobe, and mask signals Programmable CAS READ latency CL Programmable posted CAS additive latency AL Programmable CAS WRITE latency CWL Fixed burst length BL of 8 and burst chop BC of 4 via the mode register set [MRS] Selectable BC4 or BL8 on-the-fly OTF Write leveling Output driver calibration Multipurpose register T C of 4 C to +95 C 64ms, 892-cycle refresh at 4 C to +85 C 32ms at +85 C to +95 C Self refresh temperature SRT Automatic self refresh ASR Temperature-compensated self refresh TCSR mode Very low current self refresh mode at room temperature Options Marking Configuration Gig x 4 G4 52 Meg x 8 52M8 256 Meg x 6 256M6 FBGA package Pb-free x4, x8 78-ball 8mm x.5mm Rev. P DA FBGA package Pb-free x6 96-ball FBGA mm x 4mm Rev. P TW Timing cycle CL = 3 DDR Product certification Automotive A Temperature Industrial 4 C T C +95 C IT Power saving TCSR M Revision :P Notes:. Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. 2. The data sheet does not support 4 mode even though 4 mode description exists in the following sections. Table : Key Timing Parameters Speed Grade Data Rate MT/s Target t RCD- t RP-CL t RCD ns t RP ns CL ns CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 26 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications.

2 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Description Table 2: Addressing Parameter 52 Meg x Meg x 6 Configuration 64 Meg x 8 x 8 banks 32 Meg x 6 x 8 banks Refresh count 8K 8K Row address 64K A[5:] 32K A[4:] Bank address 8 BA[2:] 8 BA[2:] Column address K A[9:] K A[9:] Page size KB 2KB Figure : DDR3L-RS Part Numbers Example Part Number: MT4K52M8DA-7 AITM:P MT4K Configuration Package Speed PS Revision - { : Configuration 52 Meg x 8 52M8 256 Meg x 6 256M6 Package 78-ball 8mm x.5mm FBGA 96-ball 8mm x 4mm FBGA DA TW :P Revision Power Saving TCSR M Temperature Industrial IT -7 Speed Grade tck =.7ns, CL = 3 Certification Automotive A Note:. Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron s FBGA part marking decoder is available at CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 2 26 Micron Technology, Inc. All rights reserved.

3 Ball Assignments and Descriptions 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Ball Assignments and Descriptions Figure 2: 78-Ball FBGA x4, x8 Top View A B C D E F G H J K L M N Q Q V REFDQ ODT Q DQ DQ2 DQS NF, DQ6 DQS# Q NF, DQ4 RAS# CAS# CS# WE# BA BA2 A3 A A5 A2 A7 A9 RESET# A3 NF, NF/TDQS# DM, DM/TDQS Q DQ DQ3 NF, DQ7 NF, DQ5 CK CK# A/AP ZQ A5 V REFCA A2/BC# BA A A4 A A6 A4 A8 Q Q Q Q CKE Notes:. Ball descriptions listed in Table 3 page 5 are listed as x4, x8 if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only selectable between NF or TDQS# via MRS symbols are defined in Table 3. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 3 26 Micron Technology, Inc. All rights reserved.

4 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Ball Assignments and Descriptions Figure 3: 96-Ball FBGA x6 Top View A Q DQ3 DQ5 DQ2 Q B Q UDQS# DQ4 Q C Q DQ DQ9 UDQS DQ Q D Q Q UDM DQ8 Q E Q DQ LDM Q Q F Q DQ2 LDQS DQ DQ3 Q G Q DQ6 LDQS# Q H V REFDQ Q DQ4 DQ7 DQ5 Q J RAS# CK K ODT CAS# CK# CKE L CS# WE# A/AP ZQ M BA BA2 V REFCA N P R T A3 A5 A7 RESET# A A2 A9 A3 A2/BC# A A A4 BA A4 A6 A8 Note:. A slash defines a selectable function. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 4 26 Micron Technology, Inc. All rights reserved.

5 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA x4, x8 Ball Descriptions Symbol Type Description [5:3], A2/BC#, A, A/AP, A[9:] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit A for READ/WRITE commands, to select one location out of the memory array in the respective bank. A sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank A LOW, bank selected by BA[2:] or all banks A HIGH. The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to V REFCA. A2/BC#: When enabled in the mode register MR, A2 is sampled during READ and WRITE commands to determine whether burst chop on-the-fly will be performed HIGH = BL8 or no burst chop, LOW = BC4. See Truth Table - Command in the DDR3 SDRAM data sheet. BA[2:] Input Bank address inputs: BA[2:] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:] define which mode register MR, MR, MR2, or MR3 is loaded during the LOAD MODE command. BA[2:] are referenced to V REFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe DQS, DQS# is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables registered HIGH and disables registered LOW internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/ disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations all banks idle, or active power-down row active in any bank. CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers excluding CK, CK#, CKE, RESET#, and ODT are disabled during POWER-DOWN. Input buffers excluding CKE and RESET# are disabled during SELF REFRESH. CKE is referenced to V REFCA. CS# Input Chip select: CS# enables registered LOW and disables registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to V REFCA. DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to V REFDQ. DM has an optional use as TDQS on the x8. ODT Input On-die termination: ODT enables registered HIGH and disables registered LOW termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:], DQS, DQS#, and DM for the x8; DQ[3:], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to REFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# along with CS# define the command being entered and are referenced to V REFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH.8 and DC LOW.2 Q. RESET# assertion and desertion are asynchronous. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 5 26 Micron Technology, Inc. All rights reserved.

6 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA x4, x8 Ball Descriptions Continued Symbol Type Description DQ[3:] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:] are referenced to REFDQ. DQ[7:] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:] are referenced to V REFDQ. DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. Supply Power supply:.35v, v operational; compatible to.5v operation. Q Supply DQ power supply:.35v, v operational; compatible to.5v operation. V REFCA Supply Reference voltage for control, command, and address: V REFCA must be maintained at all times including self refresh for proper device operation. V REFDQ Supply Reference voltage for data: REFDQ must be maintained at all times excluding self refresh for proper device operation. Supply Ground. Q Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 24Ω resistor RZQ, which is tied to Q. No connect: These balls should be left unconnected the ball has no connection to the DRAM or to other balls. NF No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 6 26 Micron Technology, Inc. All rights reserved.

7 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA x6 Ball Descriptions Symbol Type Description [4:3], A2/BC#, A, A/AP, A[9:] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit A for READ/WRITE commands, to select one location out of the memory array in the respective bank. A sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank A LOW, bank selected by BA[2:] or all banks A HIGH. The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to V REFCA. A2/BC#: When enabled in the mode register MR, A2 is sampled during READ and WRITE commands to determine whether burst chop on-the-fly will be performed HIGH = BL8 or no burst chop, LOW = BC4. See Truth Table - Command in the DDR3 SDRAM data sheet. BA[2:] Input Bank address inputs: BA[2:] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:] define which mode register MR, MR, MR2, or MR3 is loaded during the LOAD MODE command. BA[2:] are referenced to V REFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe DQS, DQS# is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables registered HIGH and disables registered LOW internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations all banks idle,or active power-down row active in any bank. CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers excluding CK, CK#, CKE, RESET#, and ODT are disabled during POWER-DOWN. Input buffers excluding CKE and RESET# are disabled during SELF REFRESH. CKE is referenced to V REFCA. CS# Input Chip select: CS# enables registered LOW and disables registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to V REFCA. LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and DQS balls. LDM is referenced to V REFDQ. ODT Input On-die termination: ODT enables registered HIGH and disables registered LOW termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[5:], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x6; DQ[7:], DQS, DQS#, DM/TDQS, and NF/TDQS# when TDQS is enabled for the x8; DQ[3:], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to V REFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# along with CS# define the command being entered and are referenced to V REFCA. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 7 26 Micron Technology, Inc. All rights reserved.

8 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA x6 Ball Descriptions Continued Symbol Type Description RESET# Input Reset: RESET# is an active LOW CMOS input referenced to. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH.8 and DC LOW.2 Q. RESET# assertion and desertion are asynchronous. UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upperbyte input data is masked when UDM is sampled HIGH along with that input data during a WRITE access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and DQS balls. UDM is referenced to V REFDQ. DQ[7:] I/O Data input/output: Lower byte of bidirectional data bus for the x6 configuration. DQ[7:] are referenced to V REFDQ. DQ[5:8] I/O Data input/output: Upper byte of bidirectional data bus for the x6 configuration. DQ[5:8] are referenced to V REFDQ. LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is center-aligned to write data. Supply Power supply:.35v, v operational; compatible to.5v operation. Q Supply DQ power supply:.35v, v operational; compatible to.5v operation. V REFCA Supply Reference voltage for control, command, and address: V REFCA must be maintained at all times including self refresh for proper device operation. V REFDQ Supply Reference voltage for data: V REFDQ must be maintained at all times excluding self refresh for proper device operation. Supply Ground. Q Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 24Ω resistor RZQ, which is tied to Q. No connect: These balls should be left unconnected the ball has no connection to the DRAM or to other balls. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 8 26 Micron Technology, Inc. All rights reserved.

9 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Package Dimensions Package Dimensions Figure 4: 78-Ball FBGA x4, x8 DA.55 Seating plane.8 CTR Nonconductive overmold A.2 A 78X Ø.47 Dimensions apply to solder balls postreflow on Ø.42 SMD ball pads..5 ±. 9.6 CTR.8 TYP A B C D E F G H J K L M N Ball A ID covered by SR Ball A ID.8 TYP 6.4 CTR. ±..29 MIN 8 ±. Notes:. All dimensions are in millimeters. 2. Solder ball material: SAC % Sn, 3% Ag,.2% Cu. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 9 26 Micron Technology, Inc. All rights reserved.

10 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Package Dimensions Figure 5: 96-Ball FBGA x6 TW.55 Seating plane.8 CTR Nonconductive overmold A.2 A 96X Ø.47 Dimensions apply to solder balls postreflow on Ø.42 SMD ball pads Ball A ID covered by SR Ball A ID 4 ±. 2 CTR.8 TYP A B C D E F G H J K L M N P R T.8 TYP 6.4 CTR. ±..34 ±.5 8 ±. Notes:. All dimensions are in millimeters. 2. Material composition: Pb-free SAC % Sn, 3% Ag,.2% Cu. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 26 Micron Technology, Inc. All rights reserved.

11 Electrical Characteristics I DD Specifications 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Electrical Characteristics I DD Specifications Table 5: I DD Maximum Limits Die Rev. P Speed Bin Parameter Symbol Width Operating current : One bank ACTIVATE-to-PRECHARGE Operating current : One bank ACTIVATE-to-READ-to-PRECHARGE Precharge power-down current: Slow exit Precharge power-down current: Fast exit I DD x8 x6 DDR3L-RS -866 Unit Notes I DD x8 x6 I DD2P x8 x6 I DD2P x4, x8 Precharge quiet standby current I DD2Q x8 Precharge standby current I DD2N x8 Precharge standby ODT current I DD2NT x8 Active power-down current I DD3P x8 Active standby current I DD3N x8 Burst read operating current I DD4R x8 Burst write operating current I DD4W x8 Burst refresh current I DD5B x8 x6 x6 x6 x6 x6 x6 x6 x6 x6 ma ma ma ma ma ma ma ma ma ma ma ma Room temperature self refresh I DD6 All ma C temperature self refresh I DD6 A All ma 3 Elevated temperature self refresh I DD6 All ma 4 All ma 5 Extended temperature self refresh I DD6ET All ma 6 All ma 7 All banks interleaved read current I DD7 x8 ma x6 ma Reset current I DD8 All I DD2P + 2mA ma Notes:. T C = +85 C; SRT is disabled, ASR is disabled. Value is maximum. 2. T C Room Temperature; SRT is disabled, ASR is enabled. Value is typical. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 26 Micron Technology, Inc. All rights reserved.

12 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Electrical Characteristics I DD Specifications 3. T C +45 C; SRT is disabled, ASR is enabled. Value is typical. 4. T C = +8 C; SRT is disabled, ASR is enabled. Value is typical C < T C +8 C; SRT is disabled, ASR is enabled. Value is maximum. 6. T C = +95 C; SRT is disabled, ASR is enabled. Value is typical C < T C +95 C; SRT is disabled, ASR is enabled. Value is maximum. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 2 26 Micron Technology, Inc. All rights reserved.

13 Temperature-Compensated Self Refresh TCSR Mode Register 2 MRS Figure 6: Mode Register 2 Definition 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Temperature-Compensated Self Refresh TCSR The temperature-compensated self refresh TCSR feature substantially reduces the self refresh current I DD6. TCSR takes effect when T C is less than 45 C and the auto self refresh ASR function is enabled. ASR is required to utilize the TCSR feature and is enabled manually via mode register 2 MR2[6]. See Figure 6 page 3. Enabling ASR also automatically changes the DRAM self refresh rate from x to 2x when the case temperature exceeds 85 C. This allows the user to operate the DRAM beyond the standard 85 C limit, up to the optional extended temperature range of 95 C while in self refresh mode. When ASR is disabled and T C is C to 85 C, the self refresh mode refresh rate is assumed to be at the normal rate sometimes referred to as x refresh rate. Also, if ASR is disabled and T C is 85 C to 95 C, the user must select the SRT extended temperature self refresh rate sometimes referred to as 2x refresh rate. SRT is selected via mode register 2 MR2[7] register. See Figure 6 page 3. SPD settings should always support 5h binary in byte 3. Mode register 2 MR2 controls additional functions and features not available in the other mode registers. The ASR function is of particular interest for the DDR3L-RS SDRAM because the Micron DDR3L-RS SDRAM goes into TCSR mode when ASR has been enabled. This function is controlled via the bits shown in the figure below. BA2 BA BA A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address bus R TTWR SRT ASR CWL Mode register 2 MR2 M5 M4 Mode Register Mode register set MR Mode register set MR Mode register set 2 MR2 Mode register set 3 MR3 M M9 Dynamic ODT R TTWR R TTWR disabled RZQ/4 RZQ/2 Reserved M7 Self Refresh Temperature Normal C to 85 C Extended C to 95 C M6 Auto Self Refresh Disabled: Manual Enabled: Automatic M5 M4 M3 CAS Write Latency CWL 5 CK t CK 2.5ns 6 CK 2.5ns > t CK.875ns 7 CK.875ns > t CK.5ns 8 CK.5ns > t CK.25ns 9 CK.25ns > t CK.7ns CK.7ns > t CK.938ns Reserved Reserved Note:. MR2[7, 4:, 8, and 2:] are reserved for future use and must all be programmed to. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 3 26 Micron Technology, Inc. All rights reserved.

14 Voltage Initialization / Change 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Voltage Initialization / Change If the SDRAM is powered up and initialized for the.35v operating voltage range, voltage can be increased to the.5v operating range provided the following conditions are met See Figure 7 page 5: Just prior to increasing the.35v operating voltages, no further commands are issued, other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state. The.5V operating voltages are stable prior to issuing new commands, other than NOPs or COMMAND INHIBITs. The DLL is reset and relocked after the.5v operating voltages are stable and prior to any READ command. The ZQ calibration is performed. t ZQinit must be satisfied after the.5v operating voltages are stable and prior to any READ command. If the SDRAM is powered up and initialized for the.5v operating voltage range, voltage can be reduced to the.35v operation range provided the following conditions are met See Figure 7 page 5 : Just prior to reducing the.5v operating voltages, no further commands are issued, other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state. The.35V operating voltages are stable prior to issuing new commands, other than NOPs or COMMAND INHIBITs. The DLL is reset and relocked after the.35v operating voltages are stable and prior to any READ command. The ZQ calibration is performed. t ZQinit must be satisfied after the.35v operating voltages are stable and prior to any READ command. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 4 26 Micron Technology, Inc. All rights reserved.

15 Voltage Switching 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Voltage Initialization / Change After the DDR3L DRAM is powered up and initialized, the power supply can be altered between the DDR3L and DDR3 levels, provided the sequence in Figure 7 is maintained. Figure 7: Voltage Switching Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK, CK# t CKSRX, Q DDR3 T MIN = ns, Q DDR3L T MIN = ns T MIN = 2µs T = 5µs RESET# tis CKE T MIN = ns Valid t DLLK txpr tmrd tmrd tmrd tmod t ZQinit t IS Command Note MRS MRS MRS MRS ZQCL Note Valid BA MR2 MR3 MR MR Valid t IS t IS ODT Static LOW in case R TT,nom is enabled at time Tg, otherwise static HIGH or LOW Valid R TT Time break Don t Care Note:. From time point Td until Tk, NOP or DES commands must be applied between MRS and ZQCL commands. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 5 26 Micron Technology, Inc. All rights reserved.

16 4Gb: x8, x6 Automotive DDR3L-RS SDRAM Revision History Revision History Rev. A 8/6 Initial release for VH automotive only; Created so available for customer for -RS application. 8 S. Federal Way, P.O. Box 6, Boise, ID , Tel: Sales inquiries: Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains initial descriptions of products still under development. CCMTD gb_auto_ddr3l-rs.pdf - Rev. A 8/6 EN 6 26 Micron Technology, Inc. All rights reserved.

TwinDie 1.35V DDR3L-RS SDRAM

TwinDie 1.35V DDR3L-RS SDRAM TwinDie.35V DDR3L-RS SDRAM MT4K52M6 32 Meg x 6 x 8 Banks 8Gb: x6 TwinDie DDR3L-RS SDRAM Description Description The 8Gb (TwinDie ).35V DDR3L-RS SDRAM is a low-current self refresh version, via a TCSR feature,