2GB 4GB 8GB Module Configuration 256 x M x x x 8 (16 components)

Transcription

1 2GB WD3UN602G/WL3UN602G 4GB WD3UN604G/WL3UN604G GB WD3UN60G/WL3UN60G Features: 240-pin Unbuffered Non-ECC DDR3 DIMM for DDR3-1066, 1333, 1600 and 166MTs. JEDEC standard VDDL=1.35V (1.2V-1.45V); VDD=(1.5V (+/ V) power supply Dual rank module available in 2GB, 4GB and GB capacities. Modules are built with 16 x DDR SDRAM devices in FBGA-2(7+4) Pb-Free package Programmable CAS latency of 7, 9, 11 and 13. Fixed burst length of and burst chop of 4 via the mode register Bi-directional differential data strobe Adjustable data-output drive strength On-die termination using ODT pin SPD (Serial Presence Detect) with EEPROM Fly-by topology All contacts are gold plated Terminated command, address, and control bus ROHS compliant Standard: Figure 1: Available profile 1.11" Description: The following specification covers the family of Two-Rank Unbuffered NON-ECC DDR3 modules using x FBGA SDRAMs. Please reference Figure 1 for available layout configuration and the product ordering guide on the final page of this specification for available options including speed grade and silicon manufacturer. Speed Grades: Speed Grade Data Rate (MHz) Clock/Data Rate Latency Module Speed CL7 CL CL9 CL11 CL ns/1066MTs 7-7-7/-- PC ns/1333MTs PC ns/1600MTs PC ns/166MTs PC Address Summary Table: 2GB 4GB GB Module Configuration 256 x M x x 64 Device Configuration 12 x (16 components) 256M x (16 components) 512 x (16 components) Refresh K K K Device bank Address (BA0-BA2) (BA0-BA2) (BA0-BA2) Row Addressing A0-A13 A0-A14 A0-A15 Column Addressing A0-A9 A0-A9 A0-A9 Module Rank *Specifications are for reference purposes only and are subject to change by Wintec without notice. 2014Wintec Industries, Inc. 1

2 X64 DIMM Pin Configurations: Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF DQ NC 162 NC 2 DQ VSS 122 DQ4 43 NC DM4 3 DQ0 123 DQ NC 4 DQS4# 204 NC 4 DQ NC 165 NC 5 DQS VSS 125 DM0 46 NC DQ3 6 DQS0# 126 NC NC 7 DQ DQ39 7 DQS NC 16 RESET# DQ35 20 VSS 12 DQ6 KEY DQ44 9 DQ2 129 DQ7 49 NC 169 CKE1 90 DQ DQ45 10 DQ CKE0 170 VDD 91 DQ VSS 131 DQ12 51 VDD 171 NC/A DM5 12 DQ 132 DQ13 52 BA2 172 A14 93 DQS5# 213 NC 13 DQ NC 173 VDD 94 DQS VSS 134 DM1 54 VDD 174 A DQ46 15 DQS1# 135 NC 55 A A9 96 DQ DQ47 16 DQS A7 176 VDD 97 DQ VSS 137 DQ14 57 VDD 177 A 9 21 DQ52 1 DQ10 13 DQ15 5 A5 17 A6 99 DQ4 219 DQ53 19 DQ A4 179 VDD 100 DQ VSS 140 DQ20 60 VDD 10 A DM6 21 DQ DQ21 61 A2 11 A1 102 DQS6# 222 NC 22 DQ VDD 12 VDD 103 DQS VSS 143 DM2 63 CK1 13 VDD DQ54 24 DQS2# 144 NC 64 CK1# 14 CK0 105 DQ DQ55 25 DQS VDD 15 CK0# 106 DQ VSS 146 DQ22 66 VDD 16 VDD DQ60 27 DQ1 147 DQ23 67 VREFCA 17 NC 10 DQ56 22 DQ61 2 DQ NC 1 A0 109 DQ VSS 149 DQ2 69 VDD 19 VDD DM7 30 DQ DQ29 70 A BA1 111 DQS7# 231 NC 31 DQ BA0 191 VDD 112 DQS DM3 72 VDD 192 RAS# DQ62 33 DQS3# 153 NC 73 WE# 193 S0# 114 DQ5 234 DQ63 34 DQS CAS# 194 VDD 115 DQ DQ30 75 VDD 195 ODT VDDSPD 36 DQ DQ31 76 S1# 196 A SA0 237 SA1 37 DQ ODT1 197 VDD 11 SCL 23 SDA 3 15 NC 7 VDD 19 NC 119 SA NC 159 NC 79 NC VTT 240 VTT 40 NC DQ NC 1 DQ DQ37 NC - No Connect 2014Wintec Industries, Inc. 2

3 Pin Locations: Pin 1 Pin 4 Pin 49 Pin 120 Pin 121 Pin 16 Pin 169 Pin pin DIMM Pin Description: Pin Name Description Pin Name Description CK0 Clock s, positive line S[1:0]# Chip Selects CK0# Clock s, negative line SCL I 2 C Serial bus clock RAS# Row address strobe SDA I 2 C Serial bus Data line CAS# Column address strobe SA[2:0] I 2 C Serial Address select for EEPROM WE# Write enable A10/AP Address /Auto precharge A[9:0], A11, A[15:13] Address s A12/BC# Address /Burst chop CKE[1:0] Clock Enable BA[2:0] SDRAM Bank Address DQ0 DQ63 Data input/output VDD Power supply DQS0 DQS Data strobe input/output VREF DQ,CA Power supply for DQ, CA DQS0# DQS# Data strobe complement VDDSPD Serial EEPROM power supply DM0 DM Data mask VTT I/O Termination Supply RESET# Reset Pin EVENT# Temperature event pin ODT[1:0] On-die termination control VSS Ground NC No connection DNU/RFU Do Not Use/Reserved 2014Wintec Industries, Inc. 3

4 /Output Functional Description: Symbol Type Function CK0 CK0# CKE[1:0] S[1:0]# ODT[1:0] CK and CK# are differential system clock inputs. All the DDR3 SDRAM address/control inputs are sampled on the crossing of positive edge of CK and negative edge of CK#. DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the power down mode or the self refresh mode. Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored and previous operations continue. Rank 0 is selected by S0#; Rank 1 selected by S1#. Asserts on-die termination for DQ, DM, DQS, and DQS# signals if enabled via the DDR3 SDRAM mode register RAS#, CAS#, When sampled at the cross point of the rising edge of CK and falling edge of CK#, signals WE# CAS#, RAS#, and WE# define the operation to be executed by the SDRAM VREF DQ, VREF CA Supply Reference voltage for SSTL15 inputs BA[2:0] Selects which DDR3 SDRAM internal bank of eight is activated DQ[63:0] I/O Data bit /Output pins A[9:0], A10/AP, A11, A12/BC#, A[15:13] DM[:0] VDD, VSS Provided the row address for active commands and the column address and auto precharge bit for Read/Write to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/ identification for BL on the fly during CAS command. The address inputs also provide the op-code during Mode register set commands. Masks write data when high, issued concurrently with input data Supply Power and ground for core, I/O, SPD, Temp sensor, and ground for the module DQS[:0] I/O Positive line of the differential data strobe for input and output data DQS#[:0] I/O Negative line of the differential data strobe for input and output data SA[2:0] SDA SCL TEST RESET# Address pins used to select the serial presence detect and Temp sensor. I/O This bi-directional pin used to transfer data into or out of the SPD EEPROM and Thermal sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull-up This signal is used to clock data into and out of the SPD EEPROM and Thermal sensor. I/O The TEST pin is reserved for bus analysis tools and is not connected on normal memory module The RESET# pin is connected to the RST# pin on each DRAM. When low, all DRAMs are set to a know state 2014Wintec Industries, Inc. 4

5 Functional Block Diagram: Two Rank 256M x 64 (2GB), 512M x 64 (4GB), 1024M x 64 (GB) DDR3 Unbuffered Non- ECC DIMM (x organization) S1# S0# DQS0 DQS0# DM0 DQ[0:7] DQS1 DQS1# DM1 DQ[:15] DQ[16:23] DQS2 DQS2# DM2 DQS3 DQS3# DM3 DQ[24:31] U0 U1 U2 U3 U U9 U10 U11 DQ[32:39] DQ[40:47] DQS4 DQS4# DM4 DQS5 DQS5# DM5 DQS6 DQS6# DM6 DQ[4:55] DQ[56:63] DQS7 DQS7# DM7 U4 U5 U6 U7 U12 U13 U14 U15 BA0-BA2 A0-A15 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 RESET# BA0-BA2 to U0 - U15 A0-A15 to U0 - U15 RAS# to U0 - U15 CAS# to U0 - U15 WE# to U0 - U15 CKE to Rank 0 CKE to Rank 1 ODT to Rank 0 ODT to Rank 1 RESET# to U0 - U15 CK0 CK0# CK1 CK1# Rank 0 Rank 1 V DDSPD V DD /V DDQ V REFDQ V REFCA SCL WP SERIAL PD A0 A1 A2 To SPD To U0-U15 To U0-U15 To U0-U15 To U0-U15 SDA SA0 SA1 SA2 Notes: 1. ball on each DDR3 component is connected to an external 240 Ohm resistor that is tied to ground. Used for the calibration of the component s on-die termination and output driver. 2014Wintec Industries, Inc. 5

6 Absolute Maximum Ratings: Exposure to stresses greater than these absolute maximum rating conditions for extended periods may affect reliability of the module. Symbol Parameter Min Max Units V DD, V DD Q V DD and V DD Q supply voltage relative to V SS V V IN, V OUT Voltage on any pin relative to V SS V T STG Storage temperature (T case ) C T OPR Operating Temperature (ambient) C Note: 1. Operating Temperature T OPR is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD The Normal Temperature range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-5 C under all operating conditions 3. Some applications require operation of the extended temperature range between 5 C and 95 C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9us. It is also possible to specify a component with 1X refresh (trefi to 7.us) in the extended temperature range. b) If self-refresh option is required in the extended temperature range, then it is mandatory to either use the manual self-refresh mode with extended temperature range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional auto self-refresh mode (MR2 A6 = 1b and MR2 A7 = 0b) DC Operating Conditions: Parameter Symbol Min Typical Max Units Supply Voltage V DD V V DDL V Ground V SS V High Voltage V IH V REF V Low Voltage V IL - - V REF V 2014Wintec Industries, Inc. 6

7 Electrical Characteristics and AC Timings: V DD = +1.5V ± 0.075V, V DD Q = +1.5V ± 0.075V, V SS = 0V DDR3-1066,1333,1600,166MTs, 64-bit Parameter Symbol Unit DDR DDR DDR DDR3-166 Min. Max. Min. Max. Min. Max. Min. Max. Average Clock period tck ns Average high pulse width tch tck Average low pulse width tcl tck DQS,DQS# to DQ skew tdqsq ps DQ output hold time tqh tck DQ low-impedance time tlz ps DQ high-impedance time thz ps DQ and DM input hold time tds ps DQ and DM input setup time tdh ps DQ and DM input pulse width tdipw ps Read Preamble trpre tck Read Postamble trpst tck Output high time tqsh tck Output low time tqsl tck Write preamble twpre tck Write postamble twpst tck DQS output access time from CK,CK# tdqsck ps DQS input low/high pulse width tdqsl/h tck Write command to 1 st DQS latching transition tdqss tck DQS falling edge to CK setup time tdss tck DQS falling edge hold time from CK tdsh tck Internal Read to Precharge command delay trtp Internal write to read command delay twtr Write recovery time twr ns Mode register set command cycle time tmrd tck CAS# A to CAS# B command period tccd nck Auto Precharge write recovery+ Precharge time tdal WR+roundup(tRP/tCK(avg)) nck Active to Precharge command tras ns Active bank A to Active bank B command trrd ns Address and control input setup time tis ps Address and control input hold time tih ps Four activate window for 2KB page size tfaw ns Control and address input pulse width tipw ps 2014Wintec Industries, Inc. 7

8 V DD = +1.5V ± 0.075V, V DD Q = +1.5V ± 0.075V, V SS = 0V DDR3-1066,1333,1600,166MTs, 64-bit Parameter Symbol DDR DDR DDR DDR3-166 Unit Min. Max Min. Max. Min. Max. Min. Max.. Average periodic refresh interval trefi Read command to 1 st data taa ns Internal read or write delay time trcd ns PRE command period trp ns ACT to ACT command period trc ns ODT turn-on (Power- down mode) taonpd ps ODT turn-on taon ps ODT turn-off taof tck Note: The timing parameters are applicable to all 3 chip manufacturers Samsung, Micron, Hynix. 2014Wintec Industries, Inc.

9 Physical Dimensions Standard: 1.11" Height DDR3 Unbuffered NON-ECC DIMM Two physical rank - 16 components x organised BACK 5.250/(133.35±0.15) 0.157/(4.0) Max 1.11/(30.0) 0.74/(1.0) 0.622/(15.0) 0.433/(11.0) 0.315/(.0) Pin 1 1.5/(47.0) Pin 4 Pin 49 (0.0) 2.79/(71.0) Pin 120 (1.00) 0.050±0.004/ (1.27±0.1) FRONT SIDE Note: 1. Dimensions are in inches/(mm) 2. Outline dimensions and tolerances are in accordance with the JEDEC standard 2014Wintec Industries, Inc. 9

10 Ordering Guide: DDR3-1066, 1333, 1600, 166MTs Two-Rank x, Unbuffered Non-ECC UDIMM WD3UN6/WL3UN6 XXX YYY ZZ -AAA DDR3-1066,1333,1600,166MTs, 64-bit W D3 L3 UN6 Wintec 1.5V DDR3 SDRAM 1.35V DDR3 SDRAM Unbuffered Non-ECC, X, 16-Chips, 2-Rank XXX YYY ZZ 02G 2GB 10J CL=7 S Samsung A A-Die 04G 4GB 13L CL=9 H Hynix B B-Die 0G GB 16N CL=11 C C-Die 1P CL=13 D Q D-Die Q-Die AAA Customer reference/revision Configuration/Availability: Density Part Number Speed DRAM/Die Customer reference 2GB WD(L)3UN602G 10J, 13L, 16N, 1P ZZ 4GB WD(L)3UN604G 10J, 13L, 16N, 1P ZZ - AAA GB WD(L)3UN60G 10J, 13L, 16N, 1P ZZ Example: WD3UN60G1PSD-AAA 240-Pin DDR3 GB 166MTs Unbuffered Non-ECC DIMM Standard 1.11 Samsung D-Die for AAA WD3UN60G16NSD-AAA 240-Pin DDR3 GB 1600MTs Unbuffered Non-ECC DIMM Standard 1.11 Samsung D-Die for AAA 2014Wintec Industries, Inc. 10

11 Contact Us: Wintec Industries Sales Group 675 Sycamore Drive Milpitas, CA Ph: Fax: Revision History: Revision 1.0 (April 2012) Initial Release Revision 1.1 (November 2014) Updated Ordering Guide About Wintec Industries, Inc. Wintec, founded in 19, is headquartered in Milpitas, California. Wintec, a leading third party memory module manufacturer, specializes in a variety of module design and manufacturing, such as memory module, flash module, Handspring module, modem module, game module, etc. Besides a complete line of DDR, SDR, and EDO/FPM legacy memory modules, Wintec also distribute CPU, motherboard, peripherals, PC software, and consumer Flash products (such as MMC, SD, SMC, Compact Flash, PC Card, etc.). With excellent design engineering and manufacturing capability, Wintec provides a wide range of design and manufacturing services for our valuable customers from concept design to final product delivery. Wintec is ISO certified. Important Notice Wintec Industries, Inc. makes no representations or warranties with respect to the contents of this User Guide and specifically disclaims any implied warranties of any product design for any particular purpose. Wintec Industries, Inc. reserves the rights to revise this publication and to make changes from time to time in the content hereof without obligation of Wintec Industries, Inc. to notify any person or organization of such revisions or changes. 2014Wintec Industries, Inc. 11