MT51J256M32 16 Meg x 32 I/O x 16 banks, 32 Meg x 16 I/O x 16 banks. Options 1. Note:

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1 GDDR SGRM 8Gb: x6, x GDDR SGRM Features MTJ6M 6 Meg x I/O x 6 banks, Meg x 6 I/O x 6 banks Features = =.V ±% and.v ±% Data rate: 6.0 Gb/s, 7.0 Gb/s, 8.0 Gb/s 6 internal banks Four bank groups for t CCDL = t CK 8n-bit prefetch architecture: 6-bit per array read or write access for x; 8-bit for x6 Burst length (BL): 8 only Programmable CS latency: 7 Programmable WRITE latency: 7 Programmable CRC RED latency: Programmable CRC WRITE latency: 8 Programmable EDC hold pattern for CDR Precharge: uto option for each burst access uto refresh and self refresh modes Refresh cycles: 6,8 cycles/ms Interface: Pseudo open drain (POD-) compatible outputs: 0Ω pull-down, 60Ω pull-up On-die termination (ODT): 60Ω or 0Ω (NOM) ODT and output driver strength auto calibration with external resistor ZQ pin: 0Ω Programmable termination and driver strength offsets Selectable external or internal V REF for data inputs; programmable offsets for internal V REF Separate external V REF for address/command inputs x/x6 mode configuration set at power-up with EDC pin Single-ended interface for data, address, and command Quarter data rate differential clock inputs CK_t, CK_c for address and commands Two half data rate differential clock inputs, WCK_t and WCK_c, each associated with two data bytes (DQ, DBI_n, EDC) DDR data (WCK) and addressing (CK) SDR command (CK) Write data mask function via address bus (single/ double byte mask) Data bus inversion (DBI) and address bus inversion (BI) Digital RS lockout ddress training: ddress input monitoring via DQ pins WCKCK clock training: Phase information via EDC pins Data read and write training via read FIFO (FIFO depth = 6) Read FIFO pattern preloaded by LDFF command Direct write data load to read FIFO by WRTR command Consecutive read of read FIFO by RDTR command Read/write data transmission integrity secured by cyclic redundancy check (CRC-8) Read/write EDC on/off mode Low power modes RDQS mode on EDC pin On-die temperature sensor with readout utomatic temperature sensor controlled self refresh rate Vendor ID, FIFO depth and density info fields for identification Mirror function with MF pin Boundary scan function with SEN pin Lead-free (RoHS-compliant) and halogen-free packaging T C = 0 C to +9 C Options Marking Organization 6 Meg x (words x bits) 6M FBG package 70-ball (mm x mm) HF Timing maximum data rate 6.0 Gb/s,.0 Gb/s Gb/s, 6.0 Gb/s Gb/s, 6.0 Gb/s -80 Operating temperature Commercial (0 C T C +9 C) None Revision. Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. Products and specifications discussed herein are subject to change by Micron without notice.

2 Features Figure : Part Numbering Micron Memory MTJ 6M HF -80 : Revision Configuration 6M = 6 Meg x Package HF = 70-ball.00mm x.00mm FBG Temperature : = Commercial Data Rate -80 = 8.0 Gb/s -70 = 7.0 Gb/s -60 = 6.0 Gb/s. This Micron GDDR SGRM is available in different speed bins. The operating range and C timings of a faster speed bin are a superset of all slower speed bins. Therefore it is safe to use a faster bin device as a drop-in replacement of a slower bin device when operated within the supply voltage and frequency range of the slower bin device. FBG Part Marking Decoder Due to space limitations, FBG-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBG code, see the FBG Part Marking Decoder on Micron s web site:

3 Figure : 70-Ball FBG MF = 0 (Top View) DQ DQ0 DQ8 DQ9 B DQ DQ DQ0 DQ C EDC0 EDC D DBI0_n WCK0_t WCK0_c DBI_n E DQ DQ DQ DQ F DQ7 DQ6 DQ DQ G RS_n CS_n H 0, 0 9, B, B0, J MF RESET_n CKE_n BI_n, SEN CK_c CK_t ZQ V REFC K 8, 7, 6 B, B, L CS_n WE_n M DQ DQ0 DQ DQ N DQ9 DQ8 DQ0 DQ P DBI_n WCK_t WCK_c DBI_n R EDC EDC T DQ7 DQ6 DQ8 DQ9 U DQ DQ DQ6 DQ7 (Top view) Data ddresses GDDR Supply Ground. Balls shown with a heavy, solid outline are off in x6 mode.

4 Figure : 70-Ball FBG MF = (Top View) DQ DQ DQ6 DQ7 B DQ7 DQ6 DQ8 DQ9 C EDC EDC D DBI_n WCK_t WCK_c DBI_n E DQ9 DQ8 DQ0 DQ F DQ DQ0 DQ DQ G CS_n WE_n H 8, 7, 6 B, B, J MF RESET_n CKE_n BI_n, SEN CK_c CK_t ZQ V REFC K 0, 0 9, B, B0, L RS_n CS_n M DQ7 DQ6 DQ DQ N DQ DQ DQ DQ P DBI0_n WCK0_t WCK0_c DBI_n R EDC0 EDC T DQ DQ DQ0 DQ U DQ DQ0 DQ8 DQ9 (Top view) Data ddresses GDDR Supply Ground. Balls shown with a heavy, solid outline are off in x6 mode.

5 Table : 70-Ball FBG Ball Descriptions Symbol Type Description [:0] Input ddress inputs: Provide the row address for CTIVE commands. [6:0] (7) provide the column address and 8 defines the auto precharge bit for RED/WRITE commands, to select one location out of the memory array in the respective bank. 8 sampled during a PRECHRGE command determines whether the PRECHRGE applies to one bank (8 LOW, bank selected by B[:0]) or all banks (8 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command and the data bits during LDFF commands. [:8] are sampled with the rising edge of CK_t and [7:0], are sampled with the rising edge of CK_c. BI_n Input ddress bus inversion: Reduces the power requirements on address pins by limiting the number of address lines driving LOW to. BI_n is enabled by the corresponding BI mode register bit. B[:0] Input Bank address inputs: Define the bank to which an CTIVE, RED, WRITE, or PRE- CHRGE command is being applied. B[:0] define which mode register is loaded during the MODE REGISTER SET command. B[:0] are sampled with the rising edge of CK_t. CK_t, CK_c Input Clock: CK_t and CK_c are differential clock inputs. Command inputs are latched on the rising edge of CK_t. ddress inputs are latched on the rising edge of CK_t and the rising edge of CK_c. ll latencies are referenced to CK_t. CK_t and CK_c are externally terminated. WCK0_t, WCK0_c/ WCK_t, WCK_c Input Data Clocks: WCK_t and WCK_c are differential clocks used for write data capture and read data output. WCK0_t and WCK0_c are associated with DQ[:0], DBI0_n, DBI_n, EDC0, and EDC. WCK_t and WCK_c are associated with DQ[:6], DBI_n, DBI_n, EDC, and EDC. WCK clocks operate at nominally twice the CK clock frequency. CKE_n Input Clock enable: CKE_n enables (registered LOW) and disables (registered HIGH) internal circuitry and clocks on the device. The specific circuitry that is enabled/disabled is dependent upon the device configuration and operating mode. Taking CKE_n HIGH provides PRECHRGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE_n is synchronous for powerdown entry and exit and for self refresh entry. CKE_n must be maintained LOW throughout read and write accesses. Input buffers (excluding CKE_n) are disabled during SELF REFRESH operation. The value of CKE_n latched at power-up with RE- SET_n going HIGH determines the termination value of the address and command inputs. CS_n Input Chip select: CS_n enables (registered LOW) and disables (registered HIGH) the command decoder. ll commands are masked when CS_n is registered HIGH, but internal command execution continues. CS_n is considered part of the command code. MF Input Mirror function: CMOS input. Must be tied to or. RS_n, CS_n, WE_n Input Command inputs: RS_n, CS_n, and WE_n (along with CS_n) define the command being entered. RESET_n Input Reset: RESET_n is an active LOW CMOS input referenced to. full chip reset may be performed at any time by pulling RESET_n LOW. With RESET_n LOW all ODTs are disabled. SEN Input Scan enable: CMOS input. Must be tied to when not in use.

6 Table : 70-Ball FBG Ball Descriptions (Continued) Symbol Type Description DQ[:0] I/O Data input/output: Bidirectional -bit data bus. DBI[:0]_n I/O Data bus inversion: Reduces the DC power consumption and supply noise induced jitter on data pins. DBI0_n is associated with DQ[7:0], DBI_n with DQ[:8], DBI_n with DQ[:6], and DBI_n with DQ[:]. EDC[:0] Output Error detection code: The calculated CRC data is transmitted on these pins. In addition, these pins drive a hold pattern when idle and can be used as an RDQS function. EDC0 is associated with DQ[7:0], EDC with DQ[:8], EDC with DQ[:6], and EDC with DQ[:]. Supply Power supply:.v ±% and.v ±%. Supply DQ power supply:.v ±% and.v ±%. Isolated on the device for improved noise immunity. V REFC Supply Reference voltage for control and address: V REFC must be maintained at all times (including self refresh) for proper device operation. Supply Reference voltage for data: must be maintained at all times (including self refresh) for proper device operation. Supply Ground. Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for impedance calibration: This ball is tied to an external 0Ω resistor (ZQ), which is tied to. No connect: These balls should be left unconnected (the ball has no connection to the device or to other balls). 6

7 Package Dimensions Package Dimensions Figure : 70-Ball FBG (BG) 0. Seating plane 0.6 CTR nonconductive overmold 0. 70X Ø0.7 Dimensions apply to solder balls postreflow on Ø0.0 SMD ball pads. 0 Ball ID (covered by SR) Ball ID ±0..8 CTR 0.8 TYP B C D E F G H J K L M N P R T U 0.8 TYP. ±0. 0. CTR 0. ±0.0 ±0. Notes:. ll dimensions are in millimeters.. Solder ball material: SC-Q (9.% Sn, % g, % Bi, 0.% Cu) S. Federal Way, P.O. Box 6, Boise, ID , Tel: Sales inquiries: Micron and the Micron logo are trademarks of Micron Technology, Inc. ll other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. lthough considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 7