CA226 Advanced Computer Architecture
|
|
- Tiffany Fisher
- 5 years ago
- Views:
Transcription
1 Table of Contents Stephen Blott 1
2 MIPS MIPS is: a RISC instruction-set architecture: all ALU operations are register-register initially 32-bit, later 64-bit Its design is heavily influenced by opportunities for instruction-level parallelism: and we ll talk much more about that later 2
3 MIPS Overview We will cover: 64-bit MIPS, as simulated by the WinMIPS64 simulator there is a summary of the (WinMIPS64) MIPS instruction set here [./mips/ winmips64.html] 3
4 MIPS Basics Basics: fixed-sized, 32-bit instructions r0 is always 0 31 general-purpose integer registers (r1,, r31) 32 floating-point registers (f0,, f31) byte, half-word, word and double-word addressing displacement addressing with 16-bit displacements 4
5 Integer Loads ld r1,64(r2) lw r1,64(r3) lh r1,64(r4) lb r1,64(r5) load double word from Mem[r2+64] load word from Mem[r2+64] load half word from Mem[r2+64] load byte from Mem[r2+64] 5
6 All addressing is displacement addressing Displacement addressing: ld r1,64(r2) Direct addressing: ld r1,1024(r0) ; use r0 (always 0) Register-indirect addressing: ld r1,0(r2) ; use a displacement of 0 6
7 Immediate Addressing int i = 123; Immediate addressing: is not supported for loads/stores Note However, immediate addressing can be emulated (see anon). 7
8 Sign Extension For words, half words and bytes: loads are sign extended [ unmatched bits in the target register are padded with copies of the most significant bit from the source Therefore: the appropriate twos-compliment [ sign and value is retained for both loads and stores 8
9 Sign Extension Examples Example lb with : Example lb with :
10 Unsigned Integer Loads lwu r1,64(r3) lhu r1,128(r4) lbu r1,256(r5) load unsigned word Mem[r2+64] load unsigned half word Mem[r2+128] load unsigned byte Mem[r2+256] Note Unmatched bits are 0 (no sign extension). 10
11 Integer Stores sd r1,32(r2) sw r1,64(r3) sh r1,128(r4) sb r1,256(r5) store double word to Mem[r2+32] store word to Mem[r3+64] store half word to Mem[r4+128] store byte to Mem[r5+256] Note Unmatched bits are discarded (which is correct for both signed data and unsigned data). 11
12 Note All loads and stores use: 16 bits of displacement (although we ll come nowhere near having to worry about that) 12
13 Summary Loads and stores: displacement addressing only direct and register indirect addressing via 0-valued address components b, h, w and d variants of all load/store operation (where necessary) Loads: signed loads with sign extension unsigned loads (lwu, etc) 13
14 Floating-Point Loads/Stores There are also: bit floating-point registers (always 64-bits) Load 64-bit floating-point value: l.d f1,1024(r2) Store 64-bit floating-point value: s.d f1,1024(r2) 14
15 Integer ALU Instructions Integer arithmetic instructions are: register-register or register-immediate 64-bit arithmetic signed and unsigned variants 15
16 Register-Register Integer Arithmetic dadd r1,r2,r3 dsub r1,r2,r3 dmul r1,r2,r3 ddiv r1,r2,r3 r1 = r2 + r3 r1 = r2 - r3 r1 = r2 * r3 r1 = r2 / r3 Note ddiv is integer division, remainders are discarded. 16
17 Unsigned Integer Arithmetic daddu r1,r2,r3 dsubu r1,r2,r3 dmulu r1,r2,r3 ddivu r1,r2,r3 r1 = r2 + r3 r1 = r2 - r3 r1 = r2 * r3 r1 = r2 / r3 17
18 Immediates daddi r1,r2,100 r1 = r daddi r1,r2,-1 r1 = r2-1 18
19 Immediate Addressing (for "loads") Load in immediate value into a register: int i = 123; daddi r1,r0,123 19
20 Logical Operations (Bitwise) and r1,r2,r3 or r1,r2,r3 xor r1,r2,r3 r1 = r2 and r3 r1 = r2 or r3 r1 = r2 xor r3 andi r1,r2,1 r1 = r2 and 1 ori r1,r2,1 r1 = r2 or 1 xori r1,r2,1 r1 = r2 xor 1 20
21 Logical Shifts Table 1. Logical shifts: dsll r1,r2,1 r1 = r2 << 1 dsrl r1,r2,3 r1 = r2 >> 3 Table 2. Logical shifts (by variable amounts): dsllv r1,r2,r3 dsrlv r1,r2,r3 r1 = r2 << r3 r1 = r2 >> r3 Table 3. Arithmetic right shifts (sign extended): dsra r1,r2,1 r1 = r2 << 1 dsrav r1,r2,r3 r1 = r2 >> r3 21
22 Examples Multiply r2 by 4, result in r1: dsll r1,r2,2 Multiply r2 by 3, result in r1: dsll r1,r2,1 dadd r1,r1,r2 Divide r2 by 2, result in r1: dsrl r1,r2,1 ; or... dsra r1,r2,1 ; if r2 is unsigned (or known positive) ; general arithmetic case 22
23 Aside Note Addition, subtraction and shift instructions require considerably fewer cycles than multiplication and division, even for integers. 23
24 Set a value (set conditions) Signed: slt r1,r2,r3 ; r1 = (r2 < r3)? 1 : 0 slti r1,r2,100 ; r1 = (r2 < 100)? 1 : 0 Unsigned: sltu r1,r2,r3 ; r1 = (r2 < r3)? 1 : 0 sltiu r1,r2,100 ; r1 = (r2 < 100)? 1 : 0 Note Often used immediately before a branch. 24
25 Branches and Jumps Branches conditional changes to the programme counter Jumps unconditional changes to the programme counter 25
26 Branches and Jumps Branches typically for and while loop conditions, if statements Jumps typically loops, also subroutine, function calls 26
27 Branches Branch on equality/inequality: beq r1,r2,1024 ; branch to 1024 if r1 equals r2 bne r1,r2,1024 ; branch to 1024 if r1 doesn't equals r2 Branch on zero/not zero: beqz r1,1024 ; branch to 1024 if r1 equals 0 bnez r1,1024 ; branch to 1024 if r1 doesn't equals 0 27
28 Branch Example Example: branch iff value in r1 is less than
29 Branch Example Example: branch iff value in r1 is less than 100 slti r2,r1,100 ; set r2 iff r1 < 100 bnez r2,1024 ; branch to 1024 if r2 is set 29
30 Branch Example If statement: if ( x == 3 ) {... } // rest... ; assume x is initially in r1 daddi r3,r0,3 ; load 3 into r3 bne r1,r3,rest ; if ( x == 3 ) {... ;... rest: ; }... ; // rest 30
31 Jumps Jumps are unconditional: j 1024 ; jump to immediate 1024 jr r20 ; jump to register r20 31
32 Jump and Link (function call) For function calls: jal 1024 ; jump to 1024 jalr r20 ; jump to r20 In both cases: leave the return address (PC+4) in r31 (in this regard, r31 is also a special-purpose register) 32
33 Branches and Jumps With fixed, 32-bit instructions: it makes no sense to branch/jump to an address which is not divisible by four so target addresses are shifted left by two bits (so multiplied by four) Note This happens transparently in assembly language (where target addresses are symbolic). 33
34 Example Write a MIPS program involving a loop to: sum the numbers from 1 to 100 leaving the result in r1 Note Note to self. See mips/sum-to-100-template.s. 34
35 Example.text main: daddi r1,r0,0 ; int s = 0; daddi r2,r0,1 ; int i = 1; daddi r3,r0,101 ; int N = 101; loop: ; beq r2,r3,done ; while ( i < N ) dadd r1,r1,r2 ; s += i; daddi r2,r2,1 ; i += 1; j loop ; } done: halt ; R1 now contains 5050 (= 0x13ba) 35
36 Done <script> (function() { var mathjax = 'mathjax/mathjax.js?config=asciimath'; // var mathjax = ' var element = document.createelement('script'); element.async = true; element.src = mathjax; element.type = 'text/javascript'; (document.getelementsbytagname('head')[0] document.body).appendchild(element); })(); </script> 36
CA226 Advanced Computer Architecture
Stephen Blott Review of MIPS Instruction Set Table of Contents 1 2 Registers Memory Instructions r0 ; always 0 r1, r2,..., r31 ; general-purpose integer registers f0, f1, f2,...,
More informationMIPS Instructions: 64-bit Core Subset
MIPS Instructions: 64-bit Core Subset Spring 2008 General notes: a. R s, R t, and R d specify 64-bit general purpose registers b. F s, F t, and F d specify 64-bit floating point registers c. C d specifies
More informationCA226 Advanced Computer Architecture
Stephen Blott Today: data hazards Table of Contents 1 2 MIPS Pipeline Recall: the MIPS pipeline implements instruction level parallelism ideally, up to five instructions are executed
More informationThe MIPS Instruction Set Architecture
The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use
More informationComputer Architecture. The Language of the Machine
Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers
More informationCS3350B Computer Architecture MIPS Instruction Representation
CS3350B Computer Architecture MIPS Instruction Representation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada
More informationTSK3000A - Generic Instructions
TSK3000A - Generic Instructions Frozen Content Modified by Admin on Sep 13, 2017 Using the core set of assembly language instructions for the TSK3000A as building blocks, a number of generic instructions
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.
More informationComputer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.2: MIPS ISA -- Instruction Representation Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design,
More informationM2 Instruction Set Architecture
M2 Instruction Set Architecture Module Outline Addressing modes. Instruction classes. MIPS-I ISA. High level languages, Assembly languages and object code. Translating and starting a program. Subroutine
More informationCA226 Advanced Computer Architecture
Table of Contents Stephen Blott 1 Instruction-Set Architectures (ISAs) The functionality of a processor is defined by its: instruction-set architecture (ISA) e.g. 8086, MIPS, ARM,
More informationISA and RISCV. CASS 2018 Lavanya Ramapantulu
ISA and RISCV CASS 2018 Lavanya Ramapantulu Program Program =?? Algorithm + Data Structures Niklaus Wirth Program (Abstraction) of processor/hardware that executes 3-Jul-18 CASS18 - ISA and RISCV 2 Program
More informationComputer Architecture. MIPS Instruction Set Architecture
Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design
More informationCharacter Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21
2.9 Communication with People: Byte Data & Constants Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 32: space 33:! 34: 35: #...
More informationCPU Architecture and Instruction Sets Chapter 1
CPU Architecture and Instruction Sets Chapter 1 1 Is CPU Architecture Relevant for DBMS? CPU design focuses on speed resulting in a 55%/year improvement since 1987: If CPU performance in database code
More informationMIPS Instruction Format
MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd
More informationRISC-V Assembly and Binary Notation
RISC-V Assembly and Binary Notation L02-1 Course Mechanics Reminders Course website: http://6004.mit.edu All lectures, videos, tutorials, and exam material can be found under Information/Resources tab.
More informationCSSE 232 Computer Architecture I. I/O and Addressing
CSSE 232 Computer Architecture I I/O and Addressing 1 / 21 Class Status Reading for today 2.9-2.10, 6.6 (optional) 2 / 21 Outline I/O More memory instructions Addressing modes Jump and branch instructions
More informationMIPS Instruction Reference
Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly
More informationEE108B Lecture 3. MIPS Assembly Language II
EE108B Lecture 3 MIPS Assembly Language II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Urgent: sign up at EEclass and say if you are taking 3 or 4 units Homework
More informationMIPS Instruction Set
MIPS Instruction Set Prof. James L. Frankel Harvard University Version of 7:12 PM 3-Apr-2018 Copyright 2018, 2017, 2016, 201 James L. Frankel. All rights reserved. CPU Overview CPU is an acronym for Central
More informationECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
More informationQ1: /30 Q2: /25 Q3: /45. Total: /100
ECE 2035(A) Programming for Hardware/Software Systems Fall 2013 Exam One September 19 th 2013 This is a closed book, closed note texam. Calculators are not permitted. Please work the exam in pencil and
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationEN2910A: Advanced Computer Architecture Topic 02: Review of classical concepts
EN2910A: Advanced Computer Architecture Topic 02: Review of classical concepts Prof. Sherief Reda School of Engineering Brown University S. Reda EN2910A FALL'15 1 Classical concepts (prerequisite) 1. Instruction
More informationENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5
ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local
More informationMIPS Reference Guide
MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming
More informationReminder: tutorials start next week!
Previous lecture recap! Metrics of computer architecture! Fundamental ways of improving performance: parallelism, locality, focus on the common case! Amdahl s Law: speedup proportional only to the affected
More informationECE 30 Introduction to Computer Engineering
ECE 30 Introduction to Computer Engineering Study Problems, Set #3 Spring 2015 Use the MIPS assembly instructions listed below to solve the following problems. arithmetic add add sub subtract addi add
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA
CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationEEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture
EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction
More informationCS 4200/5200 Computer Architecture I
CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational
More informationLaboratory Exercise 6 Pipelined Processors 0.0
Laboratory Exercise 6 Pipelined Processors 0.0 Goals After this laboratory exercise, you should understand the basic principles of how pipelining works, including the problems of data and branch hazards
More informationExamples of branch instructions
Examples of branch instructions Beq rs,rt,target #go to target if rs = rt Beqz rs, target #go to target if rs = 0 Bne rs,rt,target #go to target if rs!= rt Bltz rs, target #go to target if rs < 0 etc.
More informationMACHINE LANGUAGE. To work with the machine, we need a translator.
LECTURE 2 Assembly MACHINE LANGUAGE As humans, communicating with a machine is a tedious task. We can t, for example, just say add this number and that number and store the result here. Computers have
More informationECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly)
Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions
More informationOverview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)
Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into
More informationICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation
ICS 233 COMPUTER ARCHITECTURE MIPS Processor Design Multicycle Implementation Lecture 23 1 Add immediate unsigned Subtract unsigned And And immediate Or Or immediate Nor Shift left logical Shift right
More informationISA: The Hardware Software Interface
ISA: The Hardware Software Interface Instruction Set Architecture (ISA) is where software meets hardware In embedded systems, this boundary is often flexible Understanding of ISA design is therefore important
More informationProgrammable Machines
Programmable Machines Silvina Hanono Wachman Computer Science & Artificial Intelligence Lab M.I.T. Quiz 1: next week Covers L1-L8 Oct 11, 7:30-9:30PM Walker memorial 50-340 L09-1 6.004 So Far Using Combinational
More informationFlow of Control -- Conditional branch instructions
Flow of Control -- Conditional branch instructions You can compare directly Equality or inequality of two registers One register with 0 (>,
More informationProject Part A: Single Cycle Processor
Curtis Mayberry Andrew Kies Mark Monat Iowa State University CprE 381 Professor Joseph Zambreno Project Part A: Single Cycle Processor Introduction The second part in the three part MIPS Processor design
More informationMIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support
Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible
More informationInstruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers
CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers
More informationProgrammable Machines
Programmable Machines Silvina Hanono Wachman Computer Science & Artificial Intelligence Lab M.I.T. Quiz 1: next week Covers L1-L8 Oct 11, 7:30-9:30PM Walker memorial 50-340 L09-1 6.004 So Far Using Combinational
More informationCSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.
CSCI 402: Computer Architectures Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI Recall Big endian, little endian Memory alignment Unsigned
More informationF. Appendix 6 MIPS Instruction Reference
F. Appendix 6 MIPS Instruction Reference Note: ALL immediate values should be sign extended. Exception: For logical operations immediate values should be zero extended. After extensions, you treat them
More informationCourse Administration
Fall 2017 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture 2/4 Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701 E-mail: kodi@ohio.edu
More information101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009
101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix
More informationInstruction Set Architecture. "Speaking with the computer"
Instruction Set Architecture "Speaking with the computer" The Instruction Set Architecture Application Compiler Instr. Set Proc. Operating System I/O system Instruction Set Architecture Digital Design
More informationMIPS Assembly Language. Today s Lecture
MIPS Assembly Language Computer Science 104 Lecture 6 Homework #2 Midterm I Feb 22 (in class closed book) Outline Assembly Programming Reading Chapter 2, Appendix B Today s Lecture 2 Review: A Program
More informationToday s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats
Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:
More informationECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
More informationDesign for a simplified DLX (SDLX) processor Rajat Moona
Design for a simplified DLX (SDLX) processor Rajat Moona moona@iitk.ac.in In this handout we shall see the design of a simplified DLX (SDLX) processor. We shall assume that the readers are familiar with
More informationLecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)
Lecture 2 Instructions: Language of the Computer (Chapter 2 of the textbook) Instructions: tell computers what to do Chapter 2 Instructions: Language of the Computer 2 Introduction Chapter 2.1 Chapter
More informationQuestion 0. Do not turn this page until you have received the signal to start. (Please fill out the identification section above) Good Luck!
CSC B58 Winter 2017 Final Examination Duration 2 hours and 50 minutes Aids allowed: none Last Name: Student Number: UTORid: First Name: Question 0. [1 mark] Read and follow all instructions on this page,
More informationA Model RISC Processor. DLX Architecture
DLX Architecture A Model RISC Processor 1 General Features Flat memory model with 32-bit address Data types Integers (32-bit) Floating Point Single precision (32-bit) Double precision (64 bits) Register-register
More informationMark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA
EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible
More informationMIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions
Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register
More informationbits 5..0 the sub-function of opcode 0, 32 for the add instruction
CS2 Computer Systems note 1a Some MIPS instructions More details on these, and other instructions in the MIPS instruction set, can be found in Chapter 3 of Patterson and Hennessy. A full listing of MIPS
More informationInstruction Set Architecture (ISA)
Instruction Set Architecture (ISA)... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data
More informationChapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes
Chapter 2 Instructions: Language of the Computer Adapted by Paulo Lopes Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects
More informationThomas Polzer Institut für Technische Informatik
Thomas Polzer tpolzer@ecs.tuwien.ac.at Institut für Technische Informatik Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq rs, rt, L1 if (rs == rt) branch to
More informationECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
More informationECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed.
Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions
More informationA Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3
A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU
More informationInstruction Set Principles. (Appendix B)
Instruction Set Principles (Appendix B) Outline Introduction Classification of Instruction Set Architectures Addressing Modes Instruction Set Operations Type & Size of Operands Instruction Set Encoding
More informationArithmetic for Computers
MIPS Arithmetic Instructions Cptr280 Dr Curtis Nelson Arithmetic for Computers Operations on integers Addition and subtraction; Multiplication and division; Dealing with overflow; Signed vs. unsigned numbers.
More informationCPS311 - COMPUTER ORGANIZATION. A bit of history
CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer
More informationECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed.
Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions
More informationSPIM Instruction Set
SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large
More informationece4750-tinyrv-isa.txt
========================================================================== Tiny RISC-V Instruction Set Architecture ========================================================================== # Author :
More informationCS/COE1541: Introduction to Computer Architecture
CS/COE1541: Introduction to Computer Architecture Dept. of Computer Science University of Pittsburgh http://www.cs.pitt.edu/~melhem/courses/1541p/index.html 1 Computer Architecture? Application pull Operating
More informationWeek 10: Assembly Programming
Week 10: Assembly Programming Arithmetic instructions Instruction Opcode/Function Syntax Operation add 100000 $d, $s, $t $d = $s + $t addu 100001 $d, $s, $t $d = $s + $t addi 001000 $t, $s, i $t = $s +
More informationMips Code Examples Peter Rounce
Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register $2 then
More informationMIPS Memory Access Instructions
MIPS Memory Access Instructions MIPS has two basic data transfer instructions for accessing memory lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory The data is loaded into (lw)
More informationAssembly Language. Prof. Dr. Antônio Augusto Fröhlich. Sep 2006
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 33 Assembly Language Prof. Dr. Antônio Augusto Fröhlich guto@lisha.ufsc.br http://www.lisha.ufsc.br/~guto Sep 2006 Sep 2006 Prof. Antônio
More informationChapter 2A Instructions: Language of the Computer
Chapter 2A Instructions: Language of the Computer Copyright 2009 Elsevier, Inc. All rights reserved. Instruction Set The repertoire of instructions of a computer Different computers have different instruction
More informationIntroduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University
Introduction to the MIPS Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Introduction to the MIPS The Microprocessor without Interlocked Pipeline Stages
More informationICS 233 Computer Architecture & Assembly Language. ICS 233 Computer Architecture & Assembly Language
ICS 233 Computer Architecture & Assembly Language MIPS PROCESSOR INSTRUCTION SET 1 ICS 233 Computer Architecture & Assembly Language Lecture 7 2 1 Lecture Outline MIPS Instruction I-Type Format MIPS I-type
More informationIntroduction to MIPS Processor
Introduction to MIPS Processor The processor we will be considering in this tutorial is the MIPS processor. The MIPS processor, designed in 1984 by researchers at Stanford University, is a RISC (Reduced
More informationProcedure Calling. Procedure Calling. Register Usage. 25 September CSE2021 Computer Organization
CSE2021 Computer Organization Chapter 2: Part 2 Procedure Calling Procedure (function) performs a specific task and return results to caller. Supporting Procedures Procedure Calling Calling program place
More informationProcessor. Han Wang CS3410, Spring 2012 Computer Science Cornell University. See P&H Chapter , 4.1 4
Processor Han Wang CS3410, Spring 2012 Computer Science Cornell University See P&H Chapter 2.16 20, 4.1 4 Announcements Project 1 Available Design Document due in one week. Final Design due in three weeks.
More informationEE 109 Unit 8 MIPS Instruction Set
1 EE 109 Unit 8 MIPS Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system
More informationAnne Bracy CS 3410 Computer Science Cornell University. [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon]
Anne Bracy CS 3410 Computer Science Cornell University [K. Bala, A. Bracy, E. Sirer, and H. Weatherspoon] Understanding the basics of a processor We now have the technology to build a CPU! Putting it all
More information--------------------------------------------------------------------------------------------------------------------- 1. Objectives: Using the Logisim simulator Designing and testing a Pipelined 16-bit
More informationChapter 2. Instructions: Language of the Computer. HW#1: 1.3 all, 1.4 all, 1.6.1, , , , , and Due date: one week.
Chapter 2 Instructions: Language of the Computer HW#1: 1.3 all, 1.4 all, 1.6.1, 1.14.4, 1.14.5, 1.14.6, 1.15.1, and 1.15.4 Due date: one week. Practice: 1.5 all, 1.6 all, 1.10 all, 1.11 all, 1.14 all,
More informationMIPS Assembly Programming
COMP 212 Computer Organization & Architecture COMP 212 Fall 2008 Lecture 8 Cache & Disk System Review MIPS Assembly Programming Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2
More informationThe Evolution of Microprocessors. Per Stenström
The Evolution of Microprocessors Per Stenström Processor (Core) Processor (Core) Processor (Core) L1 Cache L1 Cache L1 Cache L2 Cache Microprocessor Chip Memory Evolution of Microprocessors Multicycle
More informationECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
More informationInstructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1
Instructions: MIPS ISA Chapter 2 Instructions: Language of the Computer 1 PH Chapter 2 Pt A Instructions: MIPS ISA Based on Text: Patterson Henessey Publisher: Morgan Kaufmann Edited by Y.K. Malaiya for
More informationMIPS Assembly Language
MIPS Assembly Language Chapter 15 S. Dandamudi Outline MIPS architecture Registers Addressing modes MIPS instruction set Instruction format Data transfer instructions Arithmetic instructions Logical/shift/rotate/compare
More informationCOMPUTER ORGANIZATION AND DESIGN
COMPUTER ORGANIZATION AND DESIGN 5 th The Hardware/Software Interface Edition Chapter 2 Instructions: Language of the Computer 2.1 Introduction Instruction Set The repertoire of instructions of a computer
More informationChapter 2. Instructions: Language of the Computer
Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects in common Early computers
More informationThe MIPS R2000 Instruction Set
The MIPS R2000 Instruction Set Arithmetic and Logical Instructions In all instructions below, Src2 can either be a register or an immediate value (a 16 bit integer). The immediate forms of the instructions
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing
More informationAssembly Programming
Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming
More information5DV118 Computer Organization and Architecture Umeå University Department of Computing Science Stephen J. Hegner. Topic 3: Arithmetic
5DV118 Computer Organization and Architecture Umeå University Department of Computing Science Stephen J. Hegner Topic 3: Arithmetic These slides are mostly taken verbatim, or with minor changes, from those
More information1 5. Addressing Modes COMP2611 Fall 2015 Instruction: Language of the Computer
1 5. Addressing Modes MIPS Addressing Modes 2 Addressing takes care of where to find data instruction We have seen, so far three addressing modes of MIPS (to find data): 1. Immediate addressing: provides
More information