Near Optimal Repair Rate Built-in Redundancy Analysis with Very Small Hardware Overhead

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1 Near Optimal Repair Rate Built-in Redundancy Analysis with Very Small Hardware Overhead Woosung Lee, Keewon Cho, Jooyoung Kim, and Sungho Kang Department of Electrical & Electronic Engineering, Yonsei University, Seoul Korea Abstract As the memory density and capacity grows, it is more likely that the number of defects increases. For this reason, in order to improve memory yield, repair analysis is widely used. Built-in redundancy analysis (BIRA) is regarded as one of the solutions to improve memory yield. However, the previous BIRA approaches require large hardware overhead to achieve an optimal repair rate. This is the main obstacle to use BIRA practically. Therefore, a new BIRA is proposed to reduce the hardware overhead significantly using spare allocation probability according to the number of faults on a sparse faulty line. The experimental results show that the hardware overhead of the proposed approach can be considerably reduced with slight loss of repair rate. Therefore, it can be used as a practical solution for BIRA. Keywords Built-in redundancy analysis (BIRA), Built-in Self Repair (BISR), yield improvement 1. Introduction As the memory capacity and density become large, the operating voltage becomes small and the produced memory cells become vulnerable to noise. These reasons cause that the number of faults in a memory set is increased. Therefore, maintaining acceptable quality and yield has become a key challenge. For this reason, redundancy analysis (RA) becomes a compulsory process on production of memory Many semiconductor companies have used RA to improve memory yield. RA requires external automatic test equipment (ATE) and additional in-out pins. But built-in redundancy analysis (BIRA) does not require these burden. There are two redundancy architectures: a onedimensional (1-D) and a two-dimensional (2-D) redundancy architectures. Although the RA using the 1-D redundancy architecture uses simple operation, many spares are required to get high yield. The 2-D redundancy architecture is NPcomplete problem [1], but it can achieve high yield using less spares than the 1-D redundancy architecture. Thus, the 2-D spare architecture has been mostly adapted for the efficient spare allocation [1]-[7]. For this reason, there are many BIRA approaches to optimize trade-off among features of BIRA which are repair rate, hardware overhead and analysis speed. Repair rate and hardware overhead are key factors in BIRA. The BIRA algorithms, which have an optimal repair rate, require large hardware overhead. However, it can repair every repairable faulty pattern, such as SFCC [2], BRANCH [3], and CRESTA [4]. Although heuristic BIRA algorithms have low repair rate, such BIRA algorithms, LRM and ESP [5], use small hardware overhead and simple operation method. In order to achieve an optimal repair rate, hardware overhead is increased because all faulty information should be stored in storage elements, such as register, and content addressable memory (CAM). In this paper, the proposed BIRA uses a probabilistic approach to achieve near optimal repair rate with small hardware overhead. It does not have to save all faulty information to reduce the number of storage elements. After fault collection, the proposed BIRA perform exhaustive search using limitedly collected faulty information. Therefore, the BIRA which has a near optimal repair rate and small hardware overhead is proposed. 2. Background 2.1. Classification of Faults As the 2-D spare architecture has been adapted, allocating spares becomes NP-complete problem. For this reason, the faults should be analyzed according to the locations of faults to solve NP-complete problem. So, an incoming fault should be compared with the previously saved faults before the incoming fault is saved for reducing the number of storage elements. For the efficient fault collection, faults are classified into three types for the proposed BIRA: pivot fault, sparse faulty line, and must repair faulty line. 1) Pivot fault: an incoming fault is defined as a pivot fault when it does not share a row and a column addresses with the previously saved faults. The reason why using pivot in BIRA is to reduce hardware overhead of BIRA by sharing the row or the column addresses of the saved pivot faults with an incoming fault. Therefore, many BIRA algorithms such as ESP, SFCC and BRANCH use the pivot fault concept to reduce overall hardware overhead. 2) Sparse faulty line: a row (column) line is defined as the sparse faulty lines when the number of faults on the lines is not only larger than 1 but also smaller than the number of available column (row) spares. A row (column) sparse faulty line can be repaired by a row (column) spare. Also, the faults on the row (column) sparse faulty line can be repaired by allocating separately column (row) spares to each fault on row (column) sparse faulty line. 3) Must repair faulty line: a line is defined as a must repair faulty line when it has more faults than the number of the available spares in the different side spare from the faulty line. The sparse faulty line cannot be covered by the different side spares unlike sparse faulty line due to the insufficient number of the other side spares to cover every fault on the line. Therefore, the must repair faulty line should be covered by the same side spares with its sparse faulty line type.

2 The BIRA algorithms, which detect must repair faulty lines during fault collection, do not need to save an incoming faults that are included in the must repair faulty lines. So, the hardware overhead of BIRA using these concepts can be reduced Previous Works CRESTA has parallel redundancy analyzers. It has not only an optimal repair rate but also fast analysis speed. However, it requires very large hardware overhead by increasing the number of spares, because it makes all possible repair cases during fault collection phase. On the other hand, BRANCH and SFCC have a single redundancy analyzer. Therefore, these algorithms require smaller hardware overhead than CRESTA. However, these algorithms also require large hardware overhead to get an optimal repair rate. Because getting an optimal repair rate requires saving all of faults information in storage element. Heuristic BIRA algorithms use small hardware overhead. ESP is one of heuristic BIRA algorithms. It has a very simple and intuitive operation. So, it requires small hardware overhead, but its repair rate is rapidly decreased by increasing the number of faults. LRM is also heuristic BIRA. It requires a 2-D bitmap to save the location of faults. It allocates spares according to repair most (RM) strategy [8]. However, it has a disadvantage. The repair rate of LRM is proportional to the user-defined bitmap size Tradeoff between Repair Rate and Hardware Overhead RA uses 2-D bitmap storage structure. It does not care about pivot or must repair sparse faulty line during fault collection phase due to sufficient 2-D bitmap size. On the other hand, BIRA takes too much cost to use 2-D bitmap like RA. Therefore, some BIRA algorithms use CAM to reduce storage cells [8]. The features of CAM can search specific information and compare the saved information with the incoming fault information in a single clock cycle. Although CAM is relatively larger than register, it can set a limit of the number of faults information by using the CAM characteristics. Consequently, overall hardware size can be reduced by using CAM. Also, in order to synchronize with Built-in self-test (BIST), most BIRA algorithms use CAM to concern the pivot fault and the must repair faulty line during fault collection phase in a single clock cycle. For this reason, BIST is not interrupted by BIRA operation, and also BIRA does not have troubles with continually faulty occurrences from BIST by the CAM characteristic. SFCC and BRANCH use CAM. However, the hardware overhead is exponentially increased to achieve an optimal repair rate as mentioned above. It is inevitable the degradation of RA speed or repair rate to reduce hardware overhead. 3. The Proposed BIRA 3.1. Hardware Architecture Faults should be saved at storage to analyze how allocate row and column spares after target memory test. Figure 1 shows a fault-storing CAM structure of the proposed BIRA. It is classified into Pivot CAM (PCAM) group and Reserved Figure 1: Fault-storing CAM structure of the proposed BIRA. register (RREG) group. Pivot faults are saved at PCAM lines by comparing an incoming fault with saved faults, whereas non pivot faults are saved at the RREG that is on the same PCAM line that has sharing a row or a column address. As Figure 1, there is only one RREG for the row or column of PCAM. Immediately allocate spare when an incoming fault has same sharing row or column address with the previously saved fault on RREG. The allocation is based in probability of spares allocation that the sparse faulty line that have more faults on the line has high probability. As PCAM gets row and column faults which are independent from the existing row and column addresses on the PCAM. It preserves candidates for searching exhaustive repair cases in redundancy analysis phase. Because every pivot fault should be covered by at least a row or a column spare. Also addresses of PCAM are shared a row or column with non-pivot fault, the hardware overhead of the proposed BIRA is reduced. Because a non pivot fault uses pivot addresses that is saved in PCAM to save the non shared address of the non pivot fault. In short, a row RREG shares a column address with the address of the same line PCAM column address, while a column RREG shares a row address with the row address of the same line RREG. is the number of row spares and is the number of column spares, respectively. The number of vertical lines of the PCAM structure is the sum of +. If the number of pivots is larger than +, the memory is not repairable. For this reason, the number of PCAM is +. At least one of the row or the column of a pivot fault should be covered by either a row or a column spare. It has the same manner with collecting pivot faults of ESP. M and N is the number of rows and columns for a target memory array, respectively. To discern each fault information, the row PCAM and the column PCAM can present M and N, respectively. Enable flags show whether or not the PCAM or RREG is occupied by some fault information. And repair flags show whether a spare allocates to the corresponding row or the corresponding column faults of the pivot Fault Collection In fault collection phase, BIRA should collect faulty information according to predefined rules. After fault collection, the collected faulty information should be analyzed to deduct the repair solution. Figure 2 shows a flow of the proposed fault collection. If a fault is detected by BIST, the proposed BIRA gets the fault

3 PM UX PM UX PM UX PM UX Figure 2: Flow of a fault collection phase. addresses. The fault is saved at the PCAM if it does not share addresses with the previously saved pivot faults. But when the number of pivot faults in a faulty pattern exceeds, then the faulty pattern is unrepairable. Otherwise, an incoming fault shares the row (column) address with the PCAM, the column (row) address of the incoming fault is saved at the RREG that is on the same line with the PCAM. However, when the corresponding RREG holds another fault, there is no sufficient storage to save the incoming non-pivot fault. In this case, the proposed BIRA makes a decision of a spare allocation to the corresponding row or column of the PCAM shared with the row or column with the RREG and the incoming fault. The pre-allocation of spares except must repair spare allocation before RA phase is the heuristic property of the proposed BIRA. In SFCC and BRACH, the pre-allocation is an only must repair case. Although its repair rate is slightly degraded by allocating spares heuristically, it makes hardware overhead of the proposed BIRA considerably reduce Redundancy Analysis Phase To achieve high repair rate, an exhaustive search is required in BIRA. Although the proposed BIRA has insufficient fault data, it uses exhaustive search using a single redundancy analyzer shown Figure 3. The single analyzer is similar with BRANCH single analyzer. The BRANCH single analyzer is used to find out a redundancy analysis solution using all fault information. It tries every pivot repair combination set, because every pivot saved at PCAM should be covered by at least either a row or a column spare. Also, it adaptively allocates unused spares using Count Uncovered Faulty module. Using the pivot based exhaustive search, BRANCH can get every possible solution that can be repairable. The proposed BIRA also uses the pivot based exhaustive search. So, it can also get any solution that can be repairable using limitedly collected faults information. As a result, the proposed BIRA achieves a near optimal repair rate and the single analyzer of the proposed BIRA is simpler than that of BRANCH. Figure 3: Single redundancy analyzer. Figure 3 shows a single redundancy analyzer in the memory which has two row spares and two column spares. PCAM and RREG are connected to each multiplexer. The multiplexers connected to select a row or a column address of each pivot by the control signal shown in Figure 3. Using the control signal spares are allocated for each pivot fault as mentioned above. The width of the control signal is. Each bit value of the control signal, 1 or 0, means a row or a column of the PCAM. The values of the control signal is the corresponding a row or a col PCAM address. For example, when a control signal is 1100, 1st and 2nd PCAM is covered by row spares, while 3rd and 4th PCAM is covered by column spares. At each clock, using the values of the control signal the above process is iterated until the single redundancy analyzer finds out an RA solution. A target memory is unrepairable when all patterns of the control signal are tried. The control signal is connected to the PCAM multiplexers (PMUX), to select the repaired address among PCAM. On the contrary, it is also connected to the RREG multiplexer (), to select the unrepaired address among RREG. The unselected RREG faults are automatically repaired by covering row or column address on PCAM according to control signal. The covered addresses from PCAM and the uncovered addresses from RREG are compared in XOR gates to check whether the uncovered addresses is equal to the covered address or not. When the uncovered address is equal among the covered addresses, the uncovered address is considered. Also, a control signal pattern goes to Repair tag Check module to check whether the control signal is match with Repair tag or not. When it does not match with Repair tag Count Uncovered Sparse Faulty Line module checks the number of unused PCAM to check the number of redundancy spares. After then, unallocated spares are allocated to uncovered sparse faulty lines. A target memory is unrepairable when the every pattern of the control signal is attempted. These processes take at most!/!! clock cycles. As the proposed BIRA find the solution

4 The normalized repair rate The normalized repair rate The number of faults Sr=3, Sc=3 Sr=5, Sc=5 Branch analysis, CRESTA, SFCC ESP RM Proposed The number of faults Figure 4: The experimental result of the normalized repair rate using exhaustive search base on limited information, we can achieve high repair rate. It is called partial exhaustive search (PES) 4. Experimental Results In order to estimate the repair rate of the proposed BIRA, a BIRA simulator is used. It generates random faulty patterns and applies the simulation models of the proposed BIRA and the existing BIRA algorithms. The experiments are performed until the number of repairable cases becomes ten thousands. The normalized repair rates of the experiments are shown in Figure 4. It shows normalized repair rate (1) of ESP, RM, BRANCH and the proposed BIRA. Normalized repair rate # # (1) The proposed BIRA has a near optimal repair rate at the both different spare cases, 3 & 3 and 5 & 5. On the other hands, the repair rate of LRM and ESP rapidly decreases as the number of faults increases. Figure 5 shows the hardware overhead of ESP, RM (maximum bitmap size of LRM), BRANCH and the proposed BIRA according to the number of spares. To estimate the hardware overhead, the number of required storage elements should be calculated since the hardware overhead of BIRA is dominated by the number of storage cells. For this reason, the hardware overhead of the proposed BIRA can be estimated as Hardware overhead Branch analysis CRESTA SFCC ESP RM Proposed The number of row and column spares Figure 5: Hardware overhead estimation with different row and column spares. (M=1024, N=1024) (2). log log 3 log log (2) The hardware overhead of the proposed BIRA is small and linearly increases as the number of spares increases. However the hardware overhead of the BIRA algorithms with an optimal repair rate exponentially increases. Because, the BIRA having an optimal repair rate should save all of faults information during fault collection phase. 5. Conclusion The proposed approach uses the probability of spares allocation according to the number of spares in the sparse faulty line. The previous BIRA approaches, which has an optimal repair rate require too much hardware overhead. It can be regarded as a waste because all faults should be saved to achieve an optimal repair rate. Also, the previous heuristic BIRA approaches show the rapid decrease of repair rate as the number of faults increases. So the proposed BIRA uses a partial exhaustive search using the probability approach. It has the characteristics of both exhaustive search and heuristic spare allocation. Experimental results show that the proposed BIRA has a near optimal repair rate and a small hardware overhead. Therefore, it can be a proper solution to support the embedded memory in system-on-chip. 6. Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (No. 2012R1A2A1A ). 7. References [1] S.-K. Lu, Y.-C. Tsai, C.-H. Hsu, K.-H. Wang, and C.- W. Wu, Efficient built-in redundancy analysis for embedded memories with 2-D redundancy, IEEE Trans. Very Large Scale Integr., vol. 4, no. 1, pp , Jan [2] W. Jeong, I. Kang, K. Jin, and S. Kang, A fast built-in redundancy analysis for memories with optimal repair rate using a line-based search tree, IEEE Trans. Very Large Scale Integr. Syst., vol. 17, no. 12, pp , Dec [3] W. Jeong, J. Lee, T. Han, K. Lee, and S. Kang, An advanced BIRA for memories with an optimal repair

5 rate and fast analysis speed by using a Branch, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 12, pp , Dec [4] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, A built-in self repair analyzer (CRESTA) for embedded DRAMs in Proc. Int. Test Conf., Oct. 2000, pp [5] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, Built-in redundancy analysis for memory yield improvement, IEEE Trans. Reliab., vol. 52, no. 12, pp , Dec [6] J. R. Day, A fault-driven comprehensive redundancy algorithm, IEEE Design Test, vol. 2, no. 3, pp , Jun [7] T.-W. Tseng and J.-F. Li, A low-cost built-in redundancy-analysis scheme for word-oriented RAMs with 2-D redundancy, IEEE Trans. Very Large Scale Integr. Syst., vol. 19, no. 11, pp , Nov [8] K. Pagiamtzis and A. Sheikholeslami, Contentaddressable memory (CAM) circuits and architectures: A tutorial and survey, IEEE J. Solid-State Circuits, vol. 41, no. 3, pp , Mar

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