SoC Architecture Design Approaches

Transcription

1 Wireless Informtion Trnsmission System Lb. SoC Architecture Design Approches Hung-Chih Ching Institute of Communictions Engineering Ntionl Sun Yt-sen University

2 IP-Bsed System IC Design Block-Bsed Architecture Outline Pltform-Bsed Architecture Pltform-bsed design concepts Pltform exmples Introduction to AMBA bus

3 A Cnonicl System IC Architecture Dt Cche Instr. Cche Microprocessor Memory High Speed I/O Ctrl High Speed Bus Memory Ctrl HS IP Bus Bridge Peripherl Bus Timer Intr Ctrl GPIO UART LS IP 3

4 Fundmentl System Design Premises Discipline: The design domin need to be restricted to consistently produce sclble, supportble, nd esy to integrte designs. Simplicity: All designs hve problems. The simpler the design, the esier it is to find nd fix them. Loclity: Mking timing nd verifiction problems locl rther thn globl hs huge py-off in reducing design time. 4

5 Clssifiction of IP Soft IP (soft core/soft mcro: Synthesizble RTL. Esy to modify functionlities (if well documented. Esy to chnge processes (if well designed. Firm IP (firm core/firm mcro: Gte level netlist. Hrd to modify functionlities. Esy to chnge processes (if well designed. Hrd IP (hrd core/hrd mcro: GDSII. Very hrd to modify functionlities. Fixed processes. 5

6 IP Sources In compny IP Librries Coopertion Prtners IP Providers Free IP (typiclly buggy, need some efforts to get them work IDM Sles Chnnel / Service Provider System House (OEM/ODM Design House (fbless Siemens Motorol Toshib IP Provider Photo Msk/Foundry Service Pckging Service Testing Service 6

7 IP Reuse Issues It tkes much more effort to design n IP for reuse thn for csul reuse. Mny existing IPs were not developed for reuse. Need to develop process of designing reusble IPs. IP sources nd loylty. IP qulity nd relibility. 7

8 Configurbility: Chrcteristics of Good IP Meet the needs of mny different designs. Stndrd Interfce: Esy to integrte cores. Complince to Defensive Design Prctices: Fcilitte timing closure nd functionl correctness. Complete Set of Deliverbles: Synthesizble RTL. Complete test benches. Synthesis scripts. Documenttion. 8

9 Outline IP-Bsed System IC Design Block-Bsed Architecture Pltform-Bsed Architecture Pltform-bsed design concepts Pltform exmples Introduction to AMBA bus 9

10 Block-Bsed System IC Architecture IP0 G0 Core0 IP0* G1 IP1 IP1* IP0 G Core0 IP1 IP1/* 10

11 IP Reuse in Block-Bsed Design IP0 G0 Core0 IP0* G1 IP1* IP0 G3 Core1 IP1 IP0** G4 IP1 IP1** 11

12 IP Reuse in Block-Bsed Design IP0 G Core0 IP1 IP1/* IP0 G5 Core0 IP IP1/** 1

13 Block Connection Exmple-1 IP0 GPIO IP1 GPIO Core IP GPIO Simple but slow, limited by interfce complexity 13

14 Block Connection Exmple- IP0 IP1 Core IP register files IP3 14

15 15 Block Reuse = using squre units nd multipliers to compute, ( 8 1 GF 7 squre units nd 6 multipliers + huge combintionl logic dely! ( (( ((( (((( ((((( (((((( =

16 16 Block Reuse- using squre units nd multipliers to compute, ( 8 1 GF 1 ( (( ((( (((( ( (((( ( ((((( ( (( ((( (((( ( (((( ( (( ((( (((( ( (( ((( ( ( ( ( clock = 1 squre unit1 nd 1 multiplier + 7 clocks

17 Outline IP-Bsed System IC Design Block-Bsed Architecture Pltform-Bsed Architecture Pltform-bsed design concepts Pltform exmples Introduction to AMBA bus 17

18 Pltform-Bsed System IC Architecture Dt Cche Instr. Cche Microprocessor Memory High Speed I/O Ctrl High Speed Bus Memory Ctrl HS IP Bus Bridge Peripherl Bus Timer Intr Ctrl GPIO UART LS IP 18

19 Appliction Specific Pltform Appliction specifiction nd future rodmp. Well defined bus system, processor, memory, nd other IPs. Complete verifiction methodology. Trde off mong performnce, cost progrmmbility nd configurbility. 19

20 IP Reuse in Pltform-Bsed Design Dt Cche Instr. Cche Microprocessor Memory Plug-in nd Ply High Speed I/O Ctrl bus loding performnce limited by the slowest element High Speed Bus Memory Ctrl HS IP HS IP Bus Bridge Peripherl Bus Timer Intr Ctrl GPIO UART SPI LS IP 0

21 Pros & Cons of Pltform-Bsed Design Props: Shorten time to Mrket. Esy to locte problems in complicted system where mjor components re lredy pre-verified. Esy to extend functions from bsic design. Severl populr pltforms re lredy there for use. Cons: Predefined pltform restricts design flexibility. Hrdwre design converges. Min differentition is provided in softwre. 1

22 IP to IP Interfce (Point to Point Microprocessor Memory I/O Dt Processing Block1 Dt Processing Block Point to Point

23 IP to IP interfce (SoC Microprocessor Memory I/O Dt Processing Block1 Dt Processing Block 3

24 Point to Point with Anlog Block Microprocessor Memory USB PHY USB PIE HS IP Point to Point 4

25 Tri-Stte Bus Mster A Mster B Slve 1 Slve Slve 3 Mster A Mster B Slve 1 Slve Slve 3 Bus Bus Controller Controller Need to gurntee only one mster is ctive t the sme time during opertion Specil cres need to be tken in DFT progrm. Bus floting/keeping issues 5

26 Mux Bus Mster A Mster B Slve 1 Slve Slve 3 Mster A Mster B Slve 1 Slve Slve 3 Bus Controller Bus Controller Need dditionl routing re 6

27 On-Chip Bus Suggestions Multiplexer-bsed bus rchitecture. A single-clock-edge, flip-flop bsed rchitecture. Seprte dt nd ddress buses. Seprte control buses. Support multiple msters. 7

28 Outline IP-Bsed System IC Design Block-Bsed Architecture Pltform-Bsed Architecture Pltform-bsed design concepts Pltform exmples Introduction to AMBA bus 8

29 ARM PrimeXsys Wireless Pltform ETM MOVE ARM96 CPU SDRAM Controller Sttic Memory Interfce Vectored Interrupt Control Color LCD DMA M M S ARM I AHB ARM D AHB LCD AHB DMA 1 AHB (Periph DMA AHB (Memory EXPANSION AHB 1 EXPANSION AHB Appliction Specific IP Core APB DMA APB WATCHDOG GPIO (x4 GPIO x4 TIMERS RTC AHB/ APB SYSTEM CONTROL AHB/ APB UART SSP SIM Crd DMA APB Extensions 9

30 AWM Wireless Multimedi Pltform: 30

31 Xpert-GPS 3000 Pltform 31

32 MIPS Pltform 3

33 PowerPC CoreConnect Pltform 33

34 Outline IP-Bsed System IC Design Block-Bsed Architecture Pltform-Bsed Architecture Pltform-bsed design concepts Pltform exmples Introduction to AMBA bus 34

35 Bsic AMBA-Bsed Architecture AMBA AHB AMBA ASB AMBA APB High Performnce Pipeline opertion Multiple bus msters Burst trnsfers Split trnsctions High Performnce Pipeline opertion Multiple bus msters 35 Low power Ltched ddress nd control Simple interfce Suitble for mny peripherls

36 Introduction to AMBA AHB Fetures burst trnsfers split trnsction single-cycle bus mster hndover single-clock edge opertion non-tristte implementtion wide dt bus configurtion s(8/16/3/64/18 bits Bus Components AHB mster: A bus mster is ble to initite red nd write opertions. AHB slve: A bus slve responds to red or write opertion within given ddress rnge. AHB rbiter: The bus rbiter ensures tht only one bus mster t time is llowed to initite dt trnsfers. AHB decoder: The AHB decoder is used to decode the ddress of ech trnsfer nd provide select signl for the involved slve. 36

37 AHB Mux Bus Interconnection 37

38 Overview of AMBA AHB Opertion 1. A bus mster get grnted ccess to the bus by the bus rbiter.. The grnted bus mster strts n AHB trnsfer by driving the ddress nd control signls. Address Direction Dt width Burst Indiction 3. Every trnsfer consists of: An ddress nd control cycle One or more dt cycles 4. During trnsfer the slve shows the sttus using the response signls, HRESP[1:0]: OKAY ERROR RETRY SPLIT 38

39 AHB: Simple Trnsfer -level pipeline: The ddress phse of ny trnsfer occurs during the dt phse of the previous trnsfer 39

40 AHB: Trnsfer with Wit Sttes 40

41 AHB: Multiple Trnsfers 41

42 AHB: Trnsfer Type Four trnsfer types indicted by HTRANS[:0]: IDLE No dt trnsfer is required. BUSY The BUSY trnsfer type llows bus msters to insert IDLE cycles in the middle of bursts of trnsfers. NONSEQ Indictes the first trnsfer of burst or single trnsfer. SEQ The remining trnsfers in burst re SEQUENTIAL nd the ddress is relted to the previous trnsfer. 4

43 AHB: Trnsfer Type Exmple 43

44 AHB: Burst Opertions Burst informtion is provided using HBURST[:0]: 44

45 AHB: Four-Bit Wrpping Burst 45

46 AHB: Four-Bit Incrementing Burst 46

47 AHB: Undefined-Length Burst 47

48 AHB: Control Signls Trnsfer direction: HWITE = high for write; HWRITE = low for red Trnsfer Size: 48

49 AHB: Control Signls Protection control 49

50 AHB: Address Decoding 50

51 AHB: Trnsfer with Retry Response 51

52 AHB: Error Response 5

53 AHB: Dt Buses HWDATA[31:0]: Write dt bus; HRDATA[31:0]: Red dt bus. Active byte lnes for 3-bit little-endin dt bus 53

54 AHB: Dt Buses Active byte lnes for 3-bit big-endin dt bus 54

55 AHB: Arbitrtion HBUSREQx: Bus request from bus mster. HLOCKx: Bus lock from bus mster. HGRANTx: Grnt signl generted by the bus rbiter. HMASTER[3:0]: Current bus mster indictor. HMASTERLOCK: Lock indictor for the current bus mster. HSPLIT[15:0]: Indictor to show which bus mster cn complete SPLIT trnsction. 55

56 AHB: Grnting with No Wit Sttes 56

57 AHB: Grnting with Wit Sttes 57

58 AHB: Nrrow Slve on Wide Bus 58

59 AHB: Wide Slve on Nrrow Bus 59

60 AMBA APB AMBA APB Low power Ltched ddress nd control Simple interfce Suitble for mny peripherls 60

61 APB: Stte Digrm IDLE: The defult stte. SETUP: When trnsfer is required the bus moves into setup stte, where the pproprite select signl, PSELX, is sserted. ENABLE: The enble signl, PENABLE is sserted. 61

62 APB: Write Trnsfer 6

63 APB: Red Trnsfer 63

64 Interfcing APB to AHB: Red 64

65 Interfcing APB to AHB: Write 65

66 Summries System IC design principles- discipline, simplicity nd loclity. Properties of good IP- configurbility, stndrd interfce, complince to defensive design prctices nd complete set of deliverbles. Register files- commonly used interfce to link IPs for block-bsed design. Pltform-bsed design cn significntly shorten time to mrket compred to block-bsed design. Mux bus is recommended for on-chip bus, while tri-stte bus is recommended for onbord bus. A good Soc pltform bus exmple- AMBA.0. 66