Computer Organization and Architecture

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Campus de Gualtar 4710-057 Braga UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA Departament de Infrmática Cmputer Organizatin and Architecture 5th Editin,

Internal Memry. 5. External Memry. 6. Input/Output. 7. Operating System Supprt. III. THE CENTRAL PROCESSING UNIT. 8. Cmputer Arithmetic. 9.

Reduced Instructin Set Cmputers (RISCs). 13. Instructin-Level Parallelism and Superscalar Prcessrs. IV. THE CONTROL UNIT. 14. Cntrl Unit Operatin. 15.

1 Campus de Gualtar Braga UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA Departament de Infrmática Cmputer Organizatin and Architecture 5th Editin, 2000 by William Stallings Table f Cntents I. OVERVIEW. 1. Intrductin. 2. Cmputer Evlutin and Perfrmance. II. THE COMPUTER SYSTEM. 3. System Buses. 4. Internal Memry. 5. External Memry. 6. Input/Output. 7. Operating System Supprt. III. THE CENTRAL PROCESSING UNIT. 8. Cmputer Arithmetic. 9. Instructin Sets: Characteristics and Functins. 10. Instructin Sets: Addressing Mdes and Frmats. 11. CPU Structure and Functin. 12. Reduced Instructin Set Cmputers (RISCs). 13. Instructin-Level Parallelism and Superscalar Prcessrs. IV. THE CONTROL UNIT. 14. Cntrl Unit Operatin. 15. Micrprgrammed Cntrl. V. PARALLEL ORGANIZATION. 16. Parallel Prcessing. Appendix A: Digital Lgic. Appendix B: Prjects fr Teaching Cmputer Organizatin and Architecture. References. Glssary. Index. Acrnyms.

2 2 III. THE CENTRAL PROCESSING UNIT. 8. Cmputer Arithmetic. (19-Apr-99) Integer Representatin (8.2) Sign-Magnitude Representatin Leftmst bit is sign bit: 0 fr psitive, 1 fr negative Remaining bits are magnitude Drawbacks Additin and subtractin must cnsider bth the signs and relative magnitudes -- mre cmplex Testing fr zer must cnsider tw pssible zer representatins Tw s Cmplement Representatin Leftmst bit still indicates sign Psitive numbers exactly same as sign-magnitude Zer is nly all zeres (psitive) Negative numbers fund by taking 2 s cmplement Take cmplement f psitive versin Add 1 Integer Arithmetic (8.3) 2 s cmplement examples (with 8 bit numbers) Getting -55 Start with +55: Cmplement that: Add 1: Ttal is -55: Negating -55 Cmplement -55: Add 1: Ttal is 55 (see tp) Adding Start with -55: Add 58: Result is 3: Overflw int and ut-f sign bit is ignred Overflw Rule - if tw numbers are added, and they are bth psitive r bth negative, then verflw ccurs if and nly if the result has the ppsite sign Cnverting between different bit lengths Mve sign bit t new leftmst psitin Fill in with cpies f the sign bit Examples (8 bit -> 16 bit) +18: > : > Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

3 Multiplicatin 3 Repeated Additin Unsigned Integers Generating partial prducts, shifting, and adding Just like lnghand multiplicatin Tw s Cmplement Multiplicatin Straightfrward multiplicatin will nt wrk if either the multiplier r multiplicand are negative multiplicand wuld have t be padded with sign bit int a 2n-bit partial prduct, s that the signs wuld line up in a negative multiplier, the 1 s and 0 s wuld n lnger crrespnd t addshift s and shift-nly s Simple slutin Cnvert bth multiplier and multiplicand t psitive numbers Perfrm multiplicatin Take 2 s cmplement f result if and nly if the signs f riginal numbers were different Other methds d nt require this final transfrmatin step Bth s Algrithm Why des Bth s Algrithm wrk? Cnsider multiplying sme multiplicand M by 30: M * ( ) which wuld take 4 shift-adds f M (ne fr each 1) That is the same as multiplying M by (32-2): M * ( ) = M * ( ) - M * ( ) which wuld take: Divisin 1 shift-nly n n transitin (imagine last bit was 0) 1 shift-subtract n the transitin frm 0 t 1 3 shift-nly s n n transitin 1 shift-add n the transitin frm 1 t 0 2 shift-nly s n n transitin We can extend this methd t any number f blcks f 1 s, including blcks f unit length. Cnsider the smallest number f bits that can hld the 2 s cmplement representatin f -6: S we can clearly see that a shift-subtract at the leftmst 1-0 transitin will cause 8 t be subtracted frm the accumulated ttal, which is exactly what needs t happen! This will expand t an 8-bit representatin: The neat part is that this same (and nly) 1-0 transitin will als cause -8 t be subtracted frm the 8-bit versin! Unsigned integers Qutient Divisr Dividend Remainder Flating-Pint Representatin (8.4) Principles Using scientific ntatin, we can stre a flating pint number in 3 parts ±S * B±E : Sign Significand (r Mantissa) Expnent (The Base stays the same, s need nt be stred) Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

The sign applies t the significand. Expnents use a biased representatin, where a fixed value called the bias is subtracted frm the field t get the actual expnent.

4 The sign applies t the significand. Expnents use a biased representatin, where a fixed value called the bias is subtracted frm the field t get the actual expnent. 4 We require that numbers be nrmalized, s that the decimal in the significand is always in the same place we will chse just t the right f a leading 0 frmat will be ±0.1bbb b * 2±E thus, it is unnecessary t stre either that leading 0, r the next 1, since all numbers will have them fr the example fllwing, assume als: An 8 bit sign with a bias f 128 A 24-bit significand stred in a 23-bit field Example Ranges This cmpares t a range f 2^31 t 2^31-1 fr 2 s cmplement integers fr the same 32 bits There is mre range, but n mre individual values FP numbers are spaced unevenly alng the number line Mre densely clse t 0, less densely further frm 0 Demnstrates tradeff between range and precisin Larger expnent gives mre range, larger significand gives mre precisin IEEE Standard fr Binary Flating-Pint Arithmetic (IEEE 754) Facilitates prtability f prgrams frm ne prcessr t anther Defines bth 32-bit single and 64-bit duble frmats Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

5 5 Defines sme parameters fr extending thse frmats fr mre range r mre precisin Classes f numbers represented: Psitive r Negative Zer - an expnent f 0 tgether with a fractin f zer (sign bit determines sign). Denrmalized Numbers - an expnent f 0 tgether with a nnzer fractin. The fractin is the prtin f the significand t the right f the decimal (0 is assumed t the left). Nte that the fractin des NOT have an implied leftmst ne. Psitive r Negative Infinity - an expnent f all 1 s, tgether with a fractin f zer (sign bit determines sign). NaN (Nt a Number) - an expnent f all nes, tgether with a nn-zer fractin. Used t signal varius exceptin cnditins. Nrmalized, Nn-Zer Flating Pint Numbers - everything else. Ptential prblems: Expnent Overflw - the number is t large t be represented, may be reprted as +infinity r -infinity. Expnent Underflw - the number is t small t be represented, may be reprted as 0. Significand Underflw - during alignment f significands, digits may flw ff the right end, requiring sme frm f runding. Significand Overflw - adding tw significands with the same sign may result in a carry ut f the mst significant bit, fixed by realignment. Flating Pint Arithmetic (8.5) Additin and Subtractin Mre cmplex than multiplicatin and divisin 4 basic phases Check fr zers Align the significands Add r subtract the significands Nrmalize the result The tw perands must be transferred t registers in the ALU implicit significand bits must be made explicit expnents and significands usually stred in separate registers If subtractin, change sign f subtrahend If either perand is 0, reprt ther as result Manipulate the numbers s that the tw expnents are equal Ex. 123 x 10^ x 10^-2 = 123 x 10^ x 10^0 = x 10^0 Dne by shifting smaller number t the right Simultaneusly incrementing the expnent Stps when expnents are equal Digits lst are f relatively small imprtance If significand becmes 0, reprt ther as result The numbers are added tgether Signs are taken int accunt, s zer may result If significand verflws, the significand f the result is shifted right, and the expnent is incremented If expnent then verflws, it is reprted and peratin halted Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

6 Nrmalize the result significand digits are shifted left until the mst significant digit is nn-zer expnent is decremented fr each shift If expnent underflws, reprt it and halt Rund result and stre in prper frmat 6 Multiplicatin The tw perands must be transferred t registers in the ALU If either perand is 0, reprt 0 as result Add the expnents If a biased expnent is being used, subtract the extra bias frm the sum Check fr expnent verflw r underflw. Reprt it and halt if it ccurs. Multiply the significands Same as fr integers, but sign-magnitude representatin Prduct will be duble length f multiplier and multiplicand, but extra bits will be lst during runding Result is nrmalized and runded Same as fr additin and subtractin Thus, expnent underflw culd result Divisin The tw perands must be transferred t registers in the ALU Check fr 0 If divisr is 0, reprt errr and either set result t infinity r halt peratin if dividend is 0, reprt 0 as result Subtract divisr expnent frm dividend expnent If a biased expnent is being used, add the bias back in. Check fr expnent verflw r underflw. Reprt it and halt if it ccurs. Divide the significands Same as fr integers, but sign-magnitude representatin Result is nrmalized and runded Same as fr additin and subtractin Thus, expnent underflw culd result Precisin Cnsideratins Guard Bits Extra bits that pad ut the right end f the significand with 0 s Used t prevent lss f precisin when adding numbers which are very clse in value Example withut guard bits: * 2^ * 2^0 = * 2^ * 2^1 = * 2^1 Nrmalized t: * 2^-7 Example with guard bits: * 2^ * 2^0 = * 2^ * 2^1 = * 2^1 Nrmalized t: * 2^-8 Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

7 Ntice the rder f magnitude difference in results! Difference is wrse with base-16 architectures. Runding 4 alternative appraches with IEEE standard Rund t Nearest Result is runded t nearest representable number Default runding mde The representable value nearest t the infinitely precise result shall be delivered * if excess bits are less than half f last representable bit, rund dwn * if excess bits are half r mre f last representable bit, rund up * if they are equally clse, use the ne with LSB 0 Rund Tward + infinity and -infinity Result is runded up tward psitive infinity r Result is runded dwn tward negative infinity Useful in implementing interval arithmetic * every calculatin in a sequence is dne twice -- nce runding up, and nce runding dwn, prducing upper and lwer bunds n the result. * if resulting range is narrw enugh, then answer is sufficiently accurate * useful because hardware limitatins cause runding Rund Tward 0 Result is runded tward 0 Just simple truncatin Result is always less than r equal t the mre precise riginal value, intrducing a cnsistent dwnward bias 7 IEEE Standard fr Flating Pint Arithmetic Infinity Mst peratins invlving infinity yield infinity Signs bey usual laws -infinity -infinity yields -infinity and +infinity +infinity yields +infinity Quiet and Signaling NaN s A signaling NaN causes an exceptin (which may be handled by the prgram, r may cause an errr) A quiet NaN prpagates thrugh peratins in an expressin withut signaling an exceptin. They are prduced by: Any peratin n a signaling NaN Magnitude subtractin f infinities (where yu might expect a zer result) 0 x infinity (0 / 0) r (infinity / infinity ). Nte that x / 0 is always an exceptin. (x MOD 0) r (infinity MOD y) square-rt f x, where x < 0 Denrmalized Numbers Used in case f expnent underflw When the expnent f the result is t small ( a negative expnent with t large a magnitude) the result is denrmalized right-shifting the fractin incrementing the expnent fr each shift, until it is all nes with a final 0 Referred t as gradual underflw, use f denrmalized numbers: fills the gap between the smallest representable nn-zer number and 0 reduces the impact f expnent underflw t a level cmparable t rund ff amng the nrmalized numbers Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

Computer Organization and Architecture

Computer Organization and Architecture Campus de Gualtar 4710-057 Braga UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA Departament de Infrmática Cmputer Organizatin and Architecture 5th Editin, 2000 by William Stallings Table f Cntents I. OVERVIEW.