Computer Organization and Architecture

Transcription

1 Campus de Gualtar Braga UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA Departament de Infrmática Cmputer Organizatin and Architecture 5th Editin, 2000 by William Stallings Table f Cntents I. OVERVIEW. 1. Intrductin. 2. Cmputer Evlutin and Perfrmance. II. THE COMPUTER SYSTEM. 3. System Buses. 4. Internal Memry. 5. External Memry. 6. Input/Output. 7. Operating System Supprt. III. THE CENTRAL PROCESSING UNIT. 8. Cmputer Arithmetic. 9. Instructin Sets: Characteristics and Functins. 10. Instructin Sets: Addressing Mdes and Frmats. 11. CPU Structure and Functin. 12. Reduced Instructin Set Cmputers (RISCs). 13. Instructin-Level Parallelism and Superscalar Prcessrs. IV. THE CONTROL UNIT. 14. Cntrl Unit Operatin. 15. Micrprgrammed Cntrl. V. PARALLEL ORGANIZATION. 16. Parallel Prcessing. Appendix A: Digital Lgic. Appendix B: Prjects fr Teaching Cmputer Organizatin and Architecture. References. Glssary. Index. Acrnyms.

2 2 III. THE CENTRAL PROCESSING UNIT CPU Structure and Functin. (29-Apr-98) Prcessr Organizatin (11.1) Things a CPU must d: Fetch Instructins Interpret Instructins Fetch Data Prcess Data Write Data A small amunt f internal memry, called the registers, is needed by the CPU t fulfill these requirements Register Organizatin (11.2) Registers are at tp f the memry hierarchy. They serve tw functins: User-Visible Registers - enable the machine- r assembly-language prgrammer t minimize main-memry references by ptimizing use f registers Cntrl and Status Registers - used by the cntrl unit t cntrl the peratin f the CPU and by privileged, OS prgrams t cntrl the executin f prgrams User-Visible Registers Categries f Use General Purpse Data Address Segment pinters - hld base address f the segment in use Index registers - used fr indexed addressing and may be aut indexed Stack Pinter - a dedicated register that pints t tp f a stack. Push, pp, and ther stack instructins need nt cntain an explicit stack perand. Cnditin Cdes Design Issues Cmpletely general-purpse registers, r specialized use? Specialized registers save bits in instructins because their use can be implicit General-purpse registers are mre flexible Trend is tward use f specialized registers Number f registers prvided? Mre registers require mre perand specifier bits in instructins 8 t 32 registers appears ptimum (RISC systems use hundreds, but are a cmpletely different apprach) Register Length? Address registers must be lng enugh t hld the largest address Data registers shuld be able t hld values f mst data types Sme machines allw tw cntiguus registers fr duble-length values Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

3 Autmatic r manual save f cnditin cdes? Cnditin restre is usually autmatic upn call return Cntrl and Status Registers Saving cnditin cde registers may be autmatic upn call instructin, r may be manual 3 Essential t instructin executin Prgram Cunter (PC) Instructin Register (IR) Memry Address Register (MAR) - usually cnnected directly t address lines f bus Memry Buffer Register (MBR) - usually cnnected directly t data lines f bus Prgram Status Wrd (PSW) - als essential, cmmn fields r flags cntained include: Sign - sign bit f last arithmetic p Zer - set when result f last arithmetic p is 0 Carry - set if last p resulted in a carry int r brrw ut f a high-rder bit Equal - set if a lgical cmpare result is equality Overflw - set when last arithmetic peratin caused verflw Interrupt Enable/Disable - used t enable r disable interrupts Supervisr - indicates if privileged ps can be used Other ptinal registers Pinter t a blck f memry cntaining additinal status inf (like prcess cntrl blcks) An interrupt vectr A system stack pinter A page table pinter I/O registers Design issues Operating system supprt in CPU Hw t divide allcatin f cntrl infrmatin between CPU registers and first part f main memry (usual tradeffs apply) Example Micrprcessr Register Organizatin Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

4 4 The Instructin Cycle (11.3) Review: Basic instructin cycle cntains the fllwing sub-cycles (sme repeated) Fetch - read next instructin frm memry int CPU Execute - Interpret the pcde and perfrm the indicated peratin Interrupt - if interrupts are enabled and ne has ccurred, save the current prcess state and service the interrupt The Indirect Cycle Think f as anther instructin sub-cycle May require just anther fetch (based upn last fetch) Might als require arithmetic, like indexing Data Flw Exact sequence depends n CPU design We can indicate sequence in general terms, assuming CPU emplys: Fetch cycle data flw a memry address register (MAR) a memry buffer register (MBR) a prgram cunter (PC) an instructin register (IR) PC cntains address f next instructin t be fetched This address is mved t MAR and placed n address bus Cntrl unit requests a memry read Result is placed n data bus result cpied t MBR then mved t IR Meanwhile, PC is incremented Indirect cycle data flw After fetch, cntrl unit examines IR t see if indirect addressing is being used. If s: Rightmst n bits f MBR (the memry reference) are transferred t MAR Cntrl unit requests a memry read, t get the desired perand address int the MBR Instructin cycle data flw Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

5 Nt simple and predictable, like ther cycles Takes many frms, since frm depends n which f the varius machine instructins is in the IR May invlve transferring data amng registers read r write frm memry r I/O invcatin f the ALU 5 Interrupt cycle data flw Current cntents f PC must be saved (fr resume after interrupt), s PC is transferred t MBR t be written t memry Save lcatin s address (such as a stack ptr) is laded int MAR frm the cntrl unit PC is laded with address f interrupt rutine (s next instructin cycle will begin by fetching apprpriate instructin) Instructin Pipelining (11.4) Cncept is similar t a manufacturing assembly line Prducts at varius stages can be wrked n simultaneusly Als referred t as pipelining, because, as in a pipeline, new inputs are accepted at ne end befre previusly accepted inputs appear as utputs at the ther end Cnsider subdividing instructin prcessing int tw stages: Fetch instructin Execute instructin During executin, there are times when main memry is nt being accessed. During this time, the next instructin culd be fetched and buffered (called instructin prefetch r fetch verlap). If the Fetch and Execute stages were f equal duratin, the instructin cycle time wuld be halved. Hwever, dubling f executin time is unlikely because: Executin time is generally lnger than fetch time (it will als invlve reading and string perands, in additin t peratin executin) A cnditinal branch makes the address f the next instructin t be fetched unknwn (althugh we can minimize this prblem by fetching the next sequential instructin anyway) T gain further speedup, the pipeline must have mre stages. Cnsider the fllwing decmpsitin f instructin prcessing: Fetch Instructin (FI) Decde Instructin (DI) - determine pcde and perand specifiers Calculate Operands (CO) - calculate effective address f each surce perand Fetch Operands (FO) Execute Instructin (EI) Write Operand (WO) Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

6 6 Timing diagram, assuming 6 stages f fairly equal duratin and n branching Ntes n the diagram Each instructin is assumed t use all six stages Nt always true in reality T simplify pipeline hardware, timing is set up assuming all 6 stages will be used It assumes that all stages can be perfrmed in parallel Nt actually true, especially due t memry access cnflicts Pipeline hardware must accmmdate exclusive use f memry access lines, s delays may ccur Often, the desired value will be in cache, r the FO r WO stage may be null, s pipeline will nt be slwed much f the time If the six stages are nt f equal duratin, there will be sme waiting invlved fr shrter stages The CO (Calculate Operands) stage may depend n the cntents f a register that culd be altered by a previus instructin that is still in the pipeline It may appear that mre stages will result in even mre speedup There is sme verhead in mving data frm buffer t buffer, which increases with mre stages The amunt f cntrl lgic fr dependencies, etc. fr mving frm stage t stage increases expnentially as stages are added Cnditinal branch instructins and interrupts can invalidate several instructin fetches Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

7 Dealing with Branches 7 A variety f appraches have been taken fr dealing with cnditinal branches: Multiple Streams Instead f chsing ne f the tw instructins, replicate the initial prtins f the pipeline and allw it t fetch bth instructins, making use f tw streams. Prblems: Cntentin delays fr access t registers and memry Additinal branch instructins may enter either stream f the pipeline befre the riginal branch decisin is reslved Examples: IBM 370/168 and IBM 3033 Prefetch Branch Target The target f the branch is prefetched, in additin t the instructin fllwing the branch. The target is saved until the branch instructin is executed, s it is available withut fetching at that time. Example: IBM 360/91 Lp Buffer A small, very-high-speed memry maintained by the instructin fetch stage f the pipeline cntains the n mst recently fetched instructins, in sequence if a branch is t be taken, the buffer is checked first and the next instructin fetched frm it instead f memry Benefits It will ften cntain an instructin sequentially ahead f the current instructin, which can be used fr prefetching If a branch ccurs t a target just a few lcatins ahead f the branch instructin, the target may already be in the buffer (especially useful fr IF-THEN and IF-THEN-ELSE sequences) As implied by the name, if the buffer is large enugh t cntain all the instructins in a lp, they will nly have t be fetched frm memry nce fr all the cnsecutive iteratins f that lp Similar in principle t an instructin cache, but it nly hlds instructins in sequence smaller and thus lwer cst Examples: CDC Star-100, 6600, 7600 and CRAY-1 Branch Predictin Try t predict which branch will be taken, and prefetch that instructin Static techniques Predict Never Taken Assume that the branch will nt be taken and cntinue t fetch in sequence Examples: Mtrla and VAX 11/780 Predict Always Taken Assume that the branch will always be taken, and always fetch the branch target Studies shw that cnditinal branches are taken mre than 50% f the time NOTE: Prefetching the branch target is mre likely t cause a page fault; s paged machines may emply an avidance mechanism t reduce this penalty. Predict by Opcde Assume that the branch will be taken fr certain branch pcdes and nt fr thers Studies reprt success rates f greater than 75% Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

8 Dynamic Techniques Taken/Nt Taken Switch Delayed Branch Assume that future executins f the same branch instructin will branch the same way Assciate ne r tw extra bits with the branch instructin in high-speed memry (instructin cache r lp buffer) indicating whether it was taken the last ne r tw times Tw bits allw events like lps t nly cause ne wrng predictin instead f tw Example: IBM 3090/400 Branch Histry Table Slves prblem with Taken/Nt Taken Switch, t wit: If decisin is made t take the branch, the target instructin cannt be fetched until the target address is decded Branch Histry Table is a small cache memry assciated with the instructin fetch stage f the pipeline. Each entry has: >> the address f a branch instructin >> sme number f histry bits that recrd the state f use f that instructin >> effective address f target instructin (already calculated) r the target instructin itself Example: AMD29000 Smetimes cde can be ptimized s that branch instructins can ccur later than riginally specified Allws pipeline t stay full lnger befre ptential flushing Mre detail in chapter 12 (RISC) 8 Intel Pipelining (11.5) Uses a 5-stage pipeline Fetch - instructins are prefetched int 1 f 2 16-byte prefetch buffers. Buffers are filled as sn as ld data is cnsumed by instructin decder Instructins are variable length (1-11 bytes) On average, abut 5 instructins are fetched with each 16-byte lad Independent f rest f pipeline Decde Stage 1 Opcde and addressing mde inf is decded This inf always ccurs in first 3 bytes f instructin Decde Stage 2 Expands each pcde int cntrl signals fr the ALU Cmputatin f mre cmplex addressing mdes Execute ALU peratins cache access register update Write Back May nt be needed Updates registers and status flags mdified during Execute stage If current instructin updates memry, the cmputed value is sent t the cache and t the bus-interface write buffers at the same time With 2 decde stages, can sustain a thrughput f clse t 1 instructin per clck cycle (cmplex instructins and cnditinal branches cause slwdwn) Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000