Course on Advanced Computer Architectures

Transcription

1 Course on Advanced Computer Architectures Politecnico di Milano, June 30th, 2014 Surname (Cognome) Name (Nome) POLIMI ID Number POLIMI Address Signature (Firma) SOLUTION Prof. C. Silvano EX1A ( 2.5points) EX1B ( 2.5points) EX1C ( 2.5points) EX2A ( 5 points) EX2B ( 2.5 points) Q3 ( 5 points) Q4 ( 5 points) Q5 ( 5 points) Q6 ( 3 points) TOTAL (33 points) (33 points)

2 Course on: Advanced Computer Architectures Prof. C Silvano EXAM 30/06/2014 Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) EXERCISE 1A PIPELINE BASIC (2.5 points) Given the following loop expressed in a high level language: for (i =0; i < N; i ++) vectb[i] = vectb[i] + k1 + k2; The program has been compiled in MIPS assembly code assuming that registers $t6 and $t7 have been initialized with values 0 and 4N respectively. The symbol VECTB is a 16-bit constant. The processor clock frequency is 1.2 GHz. Let us consider the loop executed by 5-stage pipelined MIPS processor WITHOUT any optimization in the pipeline (PLEASE don t consider any inter-iteration dependencies) 1. Identify the RAW (Read After Write) Hazards in the pipeline scheme and identify the Hazard Type (Data Hazard or Control Hazard) in the last column 2. Identify in the first column the number of stalls to be inserted before each instruction (or between the stage IF and ID of each instruction) necessary to solve the hazards Num. Stalls INSTRUCTION C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 Hazard Type 3 FOR:beq $t6,$t7,end IF ID EX ME WB CNTR 3 lw $t2,vectb($t6) IF ID EX ME WB CNTR 3 addi $t2,$t2,k1 IF ID EX ME WB RAW $t2 3 addi $t2,$t2,k2 IF ID EX ME WB RAW $t2 3 sw $t2,vectb($t6) IF ID EX ME WB RAW $t2 addi $t6,$t6,4 IF ID EX ME WB 3 blt $t6,$t7, FOR IF ID EX ME WB RAW $t6 blt $t6, $t7, FOR # branch on less than Express the formula then calculate the following metrics: Instruction Count per iteration (IC): IC = 7 Number of stalls per iteration: N stall = 18 Asymptotic CPI (N cycles) : CPI AS = (IC + # stalls) / IC = (7+18) /7 = 3.57 Asymptotic Throughput (expressed in MIPS) (N cycles): MIPS AS = f CLOCK / CPI AS * 10 6 = ( ) / (CPI AS * 10 6 ) = /3.57=336 Page 1 - SOLUTION

3 Course on: Advanced Computer Architectures Prof. C Silvano EXAM 30/06/2014 Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) EXERCISE 1B PIPELINE OPTIMIZATIONS (2.5 points) Assuming there are the following optimisations in the pipeline (PLEASE don t consider any inter-iteration dependencies) - In the Register File it is possible the read and write at the same address in the same clock cycle; - Forwarding - Computation of PC and TARGET ADDRESS for branch & jump instructions anticipated in the ID stage 1. Identify the RAW (Read After Write) Hazards in the pipeline scheme and identify the Hazard Type (Data Hazard or Control Hazard) in the penultimate (one before last) column 2. Identify in the first column the number of stalls to be inserted before each instruction (or between the stage IF and ID of each instruction) necessary to solve the hazards 3. Draw the pipeline scheme by inserting the stalls to solve the given hazards and adding an ARROW to indicate the Forwarding paths used: Num. Stalls INSTRUCTION C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 Hazard Type Fowarding Path 1 FOR:beq $t6,$t7,end S IF ID EX ME WB CNTR 1 lw $t2,vectb($t6) S IF ID EX ME WB CNTR 1 addi $t2,$t2,k1 IF ID S EX ME WB RAW $t2 MEM-EX $t2 addi $t2,$t2,k2 IF S ID EX ME WB (RAW $t2) EX-EX $t2 sw $t2,vectb($t6) S IF ID EX ME WB (RAW $t2) EX-EX $t2 addi $t6,$t6,4 IF ID EX ME WB 1 blt $t6,$t7, FOR IF S ID EX ME WB RAW $t6 EX-ID $t6 Express the formula then calculate the following metrics: Number of stalls per iteration: N stall = 4 Asymptotic CPI (N cycles) : CPI AS = (IC + # stalls) / IC = (7+4) /7 = 1.57 Asymptotic Throughput (expressed in MIPS) (N cycles): MIPS AS = f CLOCK / CPI AS * 10 6 = ( ) / (CPI AS * 10 6 ) = /1.57= 764 Calculate the speedup with respect to the EXERCISE 1A: Speedup = CPI AS1A /CPI AS1B = / = 3.57 / 1.57 = 2.27 Page 2 - SOLUTION

4 Course on: Advanced Computer Architectures Prof. C Silvano EXAM 30/06/2014 Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) EXERCISE 1C PIPELINE OPTIMIZATIONS with DATA CACHE MISSES(2.5 points) Assuming there are the previous optimisations in the pipeline (EX 1B) and EACH ACCESS TO THE DATA MEMORY GENERATE A DATA CACHE MISS requiring 2 stalls to access the data memory, Draw the pipeline scheme by inserting the stalls due to the given hazards and to solve the data cache misses and adding an ARROW to indicate the Forwarding paths used: Num. INSTRUCTION C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C14 C15 C16 C17 C18 C19 C20 C21 C22 Hazard Fowarding Stalls Type Path 1 FOR:beq $t6,$t7,end S IF ID EX ME WB CNTR 3 lw $t2,vectb($t6) S IF ID EX ME S S WB CNTR + miss 1 addi $t2,$t2,k1 IF ID S S S EX ME WB RAW $t2 MEM-EX $t2 addi $t2,$t2,k2 IF S S S ID EX ME WB (RAW $t2) EX-EX $t2 2 sw $t2,vectb($t6) S S S IF ID EX ME S S WB (RAW $t2) +miss EX-EX $t2 addi $t6,$t6,4 IF ID EX S S ME WB 1 blt $t6,$t7, FOR IF S S S ID EX ME WB RAW $t6 EX-ID $t6 Express the formula then calculate the following metrics: Number of stalls per iteration: N stall = 8 (4 out of them are due to data cache misses) Asymptotic CPI (N cycles) : CPI AS = (IC + # stalls) / IC = (7+8) /7 = 2.14 Asymptotic Throughput (expressed in MIPS) (N cycles): MIPS AS = f CLOCK / CPI AS * 10 6 = ( ) / (CPI AS * 10 6 ) = /2.14 = 561 Calculate the speedup with respect to the EXERCISE 1A: Speedup = CPI AS1A /CPI AS1C = 3.57 / 2.14 = 1.67 Page 3 - SOLUTION

5 Course on: Advanced Computer Architectures Prof. C Silvano EXAM 30/06/2014 Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) EXERCISE 2A - TOMASULO (5 points) Please consider the program in the table be executed on a CPU with dynamic scheduling based on TOMASULO algorithm with: 2 RESERVATION STATIONS (RS1, RS2) + 1 LOAD/STORE unit (LDU1) with latency 6 2 RESERVATION STATIONS (RS3, RS4) + 2 ALU/BR FUs (ALU1, ALU2) with latency 2 Check STRUCTURAL hazards for RS in ISSUE phase Check RAW hazards and Check STRUCTURAL hazards for FUs in START EXECUTE phase WRITE RESULT in RESERVATION STATIONS and RF We assume 1 CDB for RF Static Branch Prediction BTFNT (BACKWARD TAKEN FORWARD NOT TAKEN) with Branch Target Buffer 1. Please complete the TOMASULO TABLE by assuming all cache HITS and considering ONE ITERATION: ISTRUZIONE Prediction ISSUE START WRITE Hazards Type RSi UNIT T /NT EXEC RESULT FOR:beq $t6,$t7,end NT RS3 ALU1 lw $t2,vectb($t6) RS1 LDU1 addi $t2,$t2,k RAW $t2 RS4 ALU2 addi $t2,$t2,k STRUCT RS3 +RAW $t2 RS3 ALU1 sw $t2,vectb($t6) (STRUCT LDU1)+RAW $t2 RS2 LDU1 addi $t6,$t6, STRUCT RS4 RS4 ALU2 blt $t6,$t7, FOR T STRUCT RS3 +(RAW $t6) RS3 ALU1 2. Express the formula then calculate the following metrics: CPI = (#clock cyles / IC) = 22/7 =3.14 IPC = 1/CPI = 1/ 3.14 = 0.32 Page 4 - SOLUTION

6 Course on: Advanced Computer Architectures Prof. C Silvano EXAM 30/06/2014 Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) EXERCISE 2B - TOMASULO (2.5 points) Please consider the program in the table be executed on a CPU with dynamic scheduling based on TOMASULO algorithm with: 2 RESERVATION STATIONS (RS1, RS2) + 1 LOAD/STORE unit (LDU1) with latency 6 3 RESERVATION STATIONS (RS3, RS4, RS5) + 2 ALU/BR FU (ALU1, ALU2) with latency 2 Check STRUCTURAL hazards for RS in ISSUE phase Check RAW hazards and Check STRUCTURAL hazards for FUs in START EXECUTE phase WRITE RESULT in RESERVATION STATIONS and RF We assume 1 CDB for RF Static Branch Prediction BTFNT (BACKWARD TAKEN FORWARD NOT TAKEN) with Branch Target Buffer 1. Please complete the TOMASULO TABLE by assuming all cache HITS and considering ONE ITERATION: ISTRUZIONE Prediction ISSUE START WRITE Hazards Type RSi UNIT T /NT EXEC RESULT FOR:beq $t6,$t7,end NT RS3 ALU1 lw $t2,vectb($t6) RS1 LDU1 addi $t2,$t2,k RAW $t2 RS4 ALU2 addi $t2,$t2,k RAW $t2 RS5 ALU1 sw $t2,vectb($t6) (STRUCT LDU1) +RAW $t2 RS2 LDU1 addi $t6,$t6, STRUCT ALU2 +STRUCT RF WR RS3 ALU2 blt $t6,$t7, FOR T STRUCT RS4+(STRUCT ALU1)+RAW $t6 RS4 ALU1 2. Express the formula then calculate the following metrics: CPI = (#clock cyles / IC) = 22/7 = 3.14 The introduction of more reservation station has been advantageous? NO Page 5 - SOLUTION

7 Course on Advanced Computer Architectures Prof. C Silvano EXAM 30/06/2014 Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) QUESTION (3): INSTRUCTION LEVEL PARALLELISM (5 points) Describe the role of Reservation Stations in Tomasulo processor architectures Describe the role of Reorder Buffer in Tomasulo processor architectures Page 6 - SOLUTION

8 Course on Advanced Computer Architectures Prof. C Silvano EXAM 30/06/2014 Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) QUESTION (4): MULTITHREADING (5 points) Explain the main concepts of multithreading Explain the main concepts of fine-grained multithreading Page 7 - SOLUTION

9 Course on Advanced Computer Architectures Prof. C Silvano EXAM 30/06/2014 Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) QUESTION (5): MULTIPROCESSORS (5 points) Describe the main concepts and benefits of distributed shared memory architectures Page 8 - SOLUTION

10 Course on Advanced Computer Architectures Prof. C Silvano EXAM 30/06/2014 Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) QUESTION (6): PERFORMANCE OF MEMORY HIERARCHY (3 points) Write the formula for the AVERAGE MEMORY ACCESS TIME (AMAT) when there is L1 cache only: Write the formula for the AVERAGE MEMORY ACCESS TIME (AMAT) when there are L1 and L2 caches: Write the formula for the GLOBAL MISS RATE for Last Level Cache (L2): Page 9 - SOLUTION