Computer Architecture CS372 Exam 3

Transcription

1 Name: Computer Architecture CS372 Exam 3 This exam has 7 pages. Please make sure you have all of them. Write your name on this page and initials on every other page now. You may only use the green card for this exam, no books, notes or calculators may be used. You have 75 minutes for this exam. Budget your time carefully. You can tear off the last page of this exam to use as reference. Please write neatly. I can t give you points if I can t read or understand your answer. Problem Possible Score Your Score 1. Performance More Performance Cache More Caches 20 Total 100

2 1) Pipelining performance - Here is a short MIPS assembly language loop. Assume that we run this code on the pipelined datapath shown on the last page. a) Find the number of clock cycles needed to execute this code, accounting for all possible stalls and flushes. Assume that $a3 is initially set to 100. (20 points) Elvis: lw $t0, 0($a1) mul $t0, $t0, $a2 lw $t1, 0($a0) add $t0, $t0, $t1 sw $t0, 0($a0) sub $a3, $a3, 1 addi $a0, $a0, 4 addi $a1, $a1, 4 bne $a3, $0, Elvis b) Show how you can re-arrange the instructions in the code above to eliminate as many stall cycles as possible. You do not need to reduce the number of flushes. (10 points) Page 2 of 6

3 2) More performance (20 points) Assume the following delays for the main functional units: Functional Unit Time delay Memory 5ns ALU 4ns Register File 3ns Given the following instructions: lw, sw, add, beq, calculate: Minimum time to perform each instruction Time required on a single-cycle datapath Time required on a multi-cycle datapath Write your answers in the table below. State any assumptions. Instruction Minimum time Single-cycle Multi-cycle lw sw add beq Page 3 of 6

4 3) Caches a) A 8-way set-associative cache has 64 byte blocks and 32-bit addresses. The cache holds 512 KB of data. Fill in the number of bits for each field in the table below. (6 points) Block offset Tag Index b) Assuming valid and dirty bits, what is the total storage required to implement this cache? (4 points) c) Given a direct-mapped cache with 4 blocks of 8 bytes, which of the following byte accesses hit? For those accesses that hit, indicate whether the hit is because of spatial locality, temporal locality, or neither in the reason column. For those accesses that miss, indicate if the miss is a conflict, capacity, or compulsory miss in the reason column. (20 points) Address (binary) Hit/Miss Reason Miss Compulsory Page 4 of 6

5 4) More Caches: A computer system has a 1 GHz processor with a split data/instruction L1 cache, and a unified L2 cache. (5 points each) a) The L2 cache uses a write-back, write-allocate strategy, and 50% of the blocks it replaces are dirty. Writing a cache block to memory and reading a cache block from memory both take 100 cycles. Compute the miss penalty for the L2 cache. b) The L2 cache has a hit time of 15 ns and a hit rate of 80%. Compute the average memory access time (AMAT) for the L2 cache. c) The I-cache has a hit time of 1 ns and a hit rate of 95%. Compute the AMAT for the I- cache. d) The D-cache has a hit rate of 98% and the same AMAT as the I-cache. Compute the hit time for the D-cache. e) Every instruction takes 1 clock cycle in addition to the time taken to fetch the instruction and access data memory (if required). If 25% of instructions in the program access data memory, compute the CPI for this program on the given processor. Page 5 of 6

6 Performance 1. Formula for computing the CPU time of a program P running on a machine X: CPU time X,P = Number of instructions executed P CPI X,P Clock cycle time X 2. CPI is the average number of clock cycles per instruction: CPI = Number of cycles needed Number of instructions executed 3. Speedup is a metric for relative performance of 2 executions: Speedup = Performance after improvement Performance before improvement = Execution time before improvement / Execution time after improvement Pipelined Datapath from class Forwarding for arithmetic operations is done from the EX/MEM and MEM/WB stages to the ALU. A hazard detection unit can insert stalls for lw instructions. Branches are assumed to be not taken, and branch determination is done in the ID stage. Equations for the ForwardA mux are given below; the ForwardB mux is similar. Page 6 of 6