AVR Instruction Set Encoding

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2 AVR Instruction Set Encoding READING 1. "AVR Instruction Set" document doc856 "The Program and Data Addressing Modes." 2. In this lecture I will teach you how to translate your assembly code into machine code and vice-versa. You can learn more about each instruction in the AVR Studio 4 Help documentation (Help - Assembler help) or "AVR Instruction Set" document doc LSL - Logical Shift Left, and LSR - Logical Shift Right in the AVR Studio, AVR Assembler Help documentation or "AVR Instruction Set" document doc Section 6.4 "General Purpose Register File" and Section 7.3 "SRAM Data Memory" except section in the ATmega328P datasheet 2 P age

3 CONTENTS Reading... 2 Contents... 3 Instruction Set Mapping... 4 ATmega328P Operand Locations... 5 Data Addressing Modes... 6 Direct Register Addressing, Single Register... 6 Direct Register Addressing, Two of 32 8-bit General Purpose Registers Rd and Rr... 7 Multiply... 8 Direct I/O Addressing (including SREG)... 9 Direct SRAM Data Addressing... 1 Immediate Indirect SRAM Data with Displacement Indirect SRAM Data Addressing with Pre-decrement and Post-increment Indirect Program Memory Addressing (Atmel Program Memory Constant Addressing) Control Transfer Direct Indirect Relative MCU Control Instructions Program Decoding Who Am I? Program Encoding Display... 2 Program Encoding Turn left Program Encoding In Forest and spitxwait Program Encoding BCD to 7-Segment Display Program Decoding SRAM Indirect Appendix A ATmega328P Instruction Set Appendix B Arduino Proto-Shield Schematic Solutions P age

4 INSTRUCTION SET MAPPING The Instruction Set of our AVR processor can be functionally divided (or classified) into: Data Transfer Instructions, Arithmetic and Logic Instructions, Bit and Bit-Test Instructions, Control Transfer (Branch) Instructions, and MCU Control Instructions. While this functional division helps you quickly find the instruction you need when you are writing a program; it does not reflect how the designers of the AVR processor mapped an assembly instruction into a 16-bit machine instruction. For this task a better way to look at the instructions is from the perspective of their addressing mode. We will divide AVR instructions into the following addressing mode types. Data Addressing Modes Direct Register Addressing, Single Register Direct Register Addressing, Two 32 General Purpose Registers Rd and Rr Direct Register Addressing, Two 16 and 8 General Purpose Registers Rd and Rr Direct I/O Addressing (including SREG) Direct I/O Addressing, First 32 I/O Registers Direct SRAM Data Addressing Immediate 8-bit Constant Immediate 6-bit and 4-bit Constant Indirect SRAM Data Addressing with Pre-decrement and Post-increment Indirect Program Memory Addressing (Atmel Program Memory Constant Addressing) Control Transfer Direct Relative, Unconditional Relative, Conditional Indirect MCU Control Instructions 4 P age

5 ATMEGA328P OPERAND LOCATIONS When selecting an addressing mode you should ask yourself where the operand is (data) located within the AVR processor. General Purpose Registers r1 r27 r29 r31 r r2... r14 r15 r16... r25 r26 r28 r3 SRAM Data Memory 248 x 8 SRAM X Y Z SRAM Address x8ff I/O Address FLASH Program Memory 16K x 16 (32 K bytes) byte 1 Application Flash Section x 16-bit Word Address (littleendian) x1 xff 16 Ext I/O Reg. 64 I/O Registers 32 Registers x6 x5f x2 x1f x x3f x Boot Flash Section 256a248 words x3fff 5 P age

6 DATA ADDRESSING MODES DIRECT REGISTER ADDRESSING, SINGLE REGISTER com Rd neg Rd swap Rd inc Rd asr Rd lsr Rd ror Rd dec Rd d dddd nnnn Register File Rd DIRECT REGISTER ADDRESSING, SINGLE REGISTER WITH BIT ADDRESS OPERAND bld bst sbrc sbrs Rd, b Rr, b Rr, b Rr, b Register File nn r/d r/d r/d r/d r/d bbb Rd 31 6 P age

7 DATA ADDRESSING MODES DIRECT REGISTER ADDRESSING, TWO OF 32 8-BIT GENERAL PURPOSE REGISTERS RD AND RR alias 16-bit move and floating point cpc Rd, Rr sbc Rd, Rr add Rd, Rr lsl Rd (let Rr = Rd) cpse Rd, Rr cp Rd, Rr sub Rd, Rr adc Rd, Rr rol Rd (let Rr = Rd) and Rd, Rr tst Rd (let Rr = Rd) eor Rd, Rr clr Rd (let Rr = Rd) or Rd, Rr mov Rd, Rr nn nnrd dddd rrrr Register File Rr Rd 31 DIRECT REGISTER ADDRESSING, TWO OF BIT GENERAL PURPOSE REGISTERS Register File movw Rd, Rr 1 dddd rrrr Rr Rr+1 Rd Rd P age

8 DATA ADDRESSING MODES Multiply DIRECT REGISTER ADDRESSING, TWO 32 GENERAL PURPOSE REGISTERS (RD AND RR) Register File mul Rd, Rr 11 11rd dddd rrrr Rr Rd 31 DIRECT REGISTER ADDRESSING, TWO 16 GENERAL PURPOSE REGISTERS (R15 < RD AND R15 < RR) Register File muls Rd, Rr 1 dddd rrrr 16 Rr Rd 31 DIRECT REGISTER ADDRESSING, TWO 8 GENERAL PURPOSE REGISTERS (R15 <RD < R24 AND R15 <RR < R24) mulsu Rd, Rr 1 fmul Rd, Rr fmuls Rd, Rr 11 fmulsu Rd, Rr 11 nddd nrrr Register File. 16 Rr Rd P age

9 DATA ADDRESSING MODES DIRECT I/O ADDRESSING (INCLUDING SREG) DIRECT I/O ADDRESSING, ONE OF 64 8-BIT I/O REGISTERS in Rd, A AAd dddd AAAA I/O Memory out A, Rr 111 1AAr rrrr AAAA DIRECT I/O ADDRESSING, ONE OF 32 8-BIT I/O REGISTERS WITH BIT ADDRESS OPERAND cbi sbic sbi sbis A, b A, b A, b A, b 11 1nn AAAA Abbb I/O Memory DIRECT I/O ADDRESSING, STATUS REGISTER (SREG) 63 SREG I alias sss bset s bclr s 111 sei cli I/O Memory T H S set seh ses clt clh cls bset bclr s s 11 1 sss sss 1 V 11 sev clv N 1 sen cln Z 1 sez clz C sec clc SREG 63 9 P age

10 DATA ADDRESSING MODES DIRECT SRAM DATA ADDRESSING lds Rd, k 11 d dddd SRAM Data Memory x8ff 248 x 8 SRAM sts k, Rr 11 1r rrrr x1 xff 16 Ext I/O Reg. x6 x5f 64 I/O Registers 32 Registers x2 x1f x 1 P age

11 DATA ADDRESSING MODES IMMEDIATE IMMEDIATE, 8-BIT CONSTANT SOURCE OPERAND WITH REGISTER DESTINATION OPERAND (R15 < RD) ldi Rd, K alias ser Rd (let K = FF 16 ) 111 KKKK dddd KKKK cpi Rd, k 11 KKKK dddd KKKK sbci Rd, K subi Rd, K ori Rd, K andi Rd, K alias sbr Rd, K cbr Rd, K (K = FF K) 1nn KKKK dddd KKKK IMMEDIATE, 6-BIT UNSIGNED CONSTANT ( 63) SOURCE OPERAND WITH ONE OF FOUR (4) 16-BIT REGISTERS (R25:R24, X, Y, Z) adiw Rd, K KKdd KKKK sbiw Rd, K KKdd KKKK IMMEDIATE, 4-BIT CONSTANT SOURCE OPERAND des K 11 1 KKKK P age

12 DATA ADDRESSING MODES INDIRECT SRAM DATA WITH DISPLACEMENT ldd Rd, Z+q ldd Rd, Y+q std Z+q, Rr std Y+q, Rr alias (q = ) ld Rd, Z ld Rd, Y st Z, Rr st Y, Rr q qqn r/d r/d r/d r/d r/d nqqq SRAM Data Memory 248 x 8 SRAM x8ff 15 + Y or Z - Register x1 xff 16 Ext I/O Reg. x6 x5f 64 I/O Registers 32 Registers x2 x1f x 12 P age

13 DATA ADDRESSING MODES INDIRECT SRAM DATA ADDRESSING WITH PRE-DECREMENT AND POST-INCREMENT 1 1 Rn Z+ -Z ld Rd, Rn 11 d dddd nnnn pop Rd 11 d dddd see lpm 11 see lpm Y+ -Y X X+ -X pop (+SP) push (SP-) st Rn, Rr 11 1r rrrr nnnn push Rr 11 1r rrrr 1111 DATA INDIRECT WITH PRE-DECREMENT 15 X,Y or Z - Register SRAM Data Memory x8ff + -1 x SRAM Data Memory DATA INDIRECT WITH POST-INCREMENT x8ff 15 X,Y or Z - Register 1 + x 13 P age

14 DATA ADDRESSING MODES INDIRECT PROGRAM MEMORY ADDRESSING (ATMEL PROGRAM MEMORY CONSTANT ADDRESSING) lpm Rd, Z see illustration 11 d dddd 1 lpm Rd, Z+ 11 d dddd 11 lpm note: R implied Flash Program Memory x 15 Z - Register 7 7 x3fff select 7 8 Rd 14 P age

15 CONTROL TRANSFER DIRECT All control transfer addressing modes modify the program counter. 1 jmp k call k k 11nk color key Flash Program Memory ATmega Family ATmega328P 4 M words 16 K words 15 x 15 PC x3fff 15 P age

16 CONTROL TRANSFER INDIRECT nnn opcode ijmp eijmp ret icall reti eicall notes see illustration n/a to 328P PC M[SP + 1] see illustration PC M[SP + 1] n/a to 328P n n 1n Flash Program Memory x Z - Register 15 PC x3fff 16 P age

17 UNCONDITIONAL CONTROL TRANSFER RELATIVE 1 rjmp k rcall k Flash Program Memory 11n x 15 PC + CONDITIONAL 1 brbs s, k brbc s, k x3fff 1111 nkk ksss NOTES SREG I T H S V N Z C sss brie k brts k brhs k brlt k brvs k brmi k breq k brbs s, k alias brbc s, k brid k brtc k brhc k brge k brvc k brpl k brne k brcs k brlo k brcc k brsh k 1. See Register Direct Addressing for encoding of skip register bit set/clear instructions sbrc and sbrs. 2. See I/O Direct Addressing for encoding of skip I/O register bit set/clear instructions sbis and sbic. 17 P age

18 MCU CONTROL INSTRUCTIONS sleep break wdr nn 1 nop 18 P age

19 PROGRAM DECODING WHO AM I? Addr Machine Instruction Who_Am_I #1: 24 9a5d, // I/O direct d, // I/O direct Who_Am_I #2: 1f8 934f // Indirect SRAM Data Addressing 1f9 b74f, // I/O Direct 1fa 93f // Indirect SRAM Data Addressing 1fb , 1fd 91 12, // Direct SRAM Data Addressing // Direct SRAM Data Addressing 1ff 238, // Direct Register Addressing, 2 91f // Indirect SRAM Data Addressing 21 bf4f, // I/O Direct f // Indirect SRAM Data Addressing P age

20 display: : lds work,imager lds spi7seg,imaged or spi7seg,work call spitx : ret PROGRAM ENCODING DISPLAY 2 P age

21 PROGRAM ENCODING TURN LEFT ; ; Turn Left turnleft: push reg_f in reg_f,sreg : lds work, dir // x = work bit 1, y = work bit bst work, // store y into T bld work1,1 // load dir.1 from T (dir.1 = y) com work // store /x into T bst work,1 bld work1, // load dir. from T (dir. = /x) sts dir, work1 : out SREG, reg_f pop reg_f ret 21 P age

22 PROGRAM ENCODING IN FOREST AND SPITXWAIT inforest: Address Machine Instruction 131 ldi ZL,low(table<<1) // load address of look-up : 2e8 lds work, row // SRAM row address = 11 2e9 2ea cpi work, xff 2eb breq yes 2ec clr cppreg // Compare to eor cppreg, cppreg 2ed rjmp endforest yes: 2ee ser cppreg // compare to ldi cppreg, xff endforest: : 2f3 ret spitxwait: 112 in work,spsr 113 bst work,spif 114 brtc spitxwait 115 ret 22 P age

23 PROGRAM ENCODING BCD TO 7-SEGMENT DISPLAY Program Memory Indirect is great for implementing look-up tables located in Flash program memory including decoders (gray code binary, hex seven segment, ) In this example I build a 7-segment decoder in software. BCD_to_7SEG: Address Machine Instruction 131 ldi ZL,low(table<<1) // load address of look-up 132 ldi ZH,high(table<<1) 133 clr r1 134 add ZL, r adc ZH, r1 136 lpm spi7seg, Z 137 ret 138 table: DB b111111, b11, b P age

24 PROGRAM DECODING SRAM INDIRECT Write and encode a program to set to ASCII Space Character (x2), all the bytes in a 64-byte Buffer. 24 P age

25 APPENDIX A ATMEGA328P INSTRUCTION SET 1 1 Source: ATmega328P Data Sheet Chapter 31 Instruction Set Summary 25 P age

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28 APPENDIX B ARDUINO PROTO-SHIELD SCHEMATIC 28 P age

29 pulse: Who Am I #1 SOLUTIONS 24 9a5d sbi PORTD,dff_clk // Set clock (2 clock cycles) d cbi PORTD,dff_clk // Clear clock (2 clock cycles) ret hitwall: Who Am I #2 1f8 934f push reg_f // push any flags or registers modified 1f9 b74f in reg_f,sreg 1fa 93f push work 1fb lds cppreg,imaged 1fd lds work,imager 1ff 238 and cppreg,work 2 91f pop work // pop any flags or registers placed on the stack 21 bf4f out SREG, reg_f f pop reg_f ret display: 19a 934f push reg_f 19b b74f in reg_f,sreg 19c 93f push work 29 P age

30 19d lds work,imager 19f lds spi7seg,imaged 1a1 2a8 or spi7seg,work 1a2 94e 19 call spitx 1a4 91f 1a5 bf4f 1a6 914f 1a7 958 pop work out SREG,reg_F pop reg_f ret turnleft: 1b9 934f push reg_f 1ba b74f in reg_f,sreg 1bb 93f 1bc 931f push work push work1 1bd 91 1 lds work, dir // x = work bit 1, y = work bit 1bf fb bst work, // store y into T 1c f911 bld work1,1 // load dir.1 from T (dir.1 = y) 1c1 95 com work // store /x into T 1c2 fb1 bst work,1 1c3 f91 bld work1, // load dir. from T (dir. = /x) 1c sts dir, work1 3 P age

31 1c6 911f 1c7 91f 1c8 bf4f 1c9 914f 1ca 958 pop work1 pop work out SREG, reg_f pop reg_f ret inforest: 2e5 92ff push reg_f // push any flags or registers modified 2e6 b6ff in reg_f,sreg 2e7 93f push work 2e lds work,row 2ea 3ff 2eb f11 cpi work,xff breq yes 2ec 2788 clr cppreg // no 2ed c1 rjmp endforest yes: 2ee ef8f ser cppreg endforest: 2ef 2799 clr r25 // zero-extended to 16-bits for C++ call 2f 91f pop work // pop any flags or registers placed on the stack 2f1 beff out SREG,reg_F 31 P age

32 2f2 9ff 2f3 958 pop reg_f ret spitxwait: ; Wait for transmission complete 112 b5d in r16,spsr 113 fb7 bst r16,spif 114 f7ee brtc spitxwait ret BCD_to_7SEG: 131 e7e ldi ZL,low(table<<1) // load address of look-up 132 ef2 ldi ZH,high(table<<1) clr r1 134 fe add ZL, r df1 adc ZH, r lpm spi7seg, Z ret e 139 6d6d table:.db b111111, b11, b11111, b P age