68HC11 PROGRAMMER'S MODEL

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Michael Bennett
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1 8H11 PROGRMMER'S MODEL s (,, and D) s and are general-purpose 8-bit accumulators used to hold operands and results of arithmetic calculations or data manipulations. Some instructions treat the combination of these two 8-bit accumulators as a 1-bit double accumulator (accumulator D). Index Registers (X and Y) The 1-bit index registers X and Y are used for indexed aressing mode. In most cases, instructions involving index register Y take one extra byte of object code and one extra cycle of execution time compared to the equivalent instruction using index register X. (SP) The M8H11 PU automatically supports a program stack with this 1-bit register. This stack may be located anywhere in the -Kbyte aress space and may be any size up to the amount of memory available in the system. Program ounter (P) The program counter is a 1-bit register that holds the aress of the next instruction to be executed. ondition ode Register (R) The H bit indicates a carry from bit during an aition operation. The N bit reflects the state of the most significant bit (MS) of a result. The Z bit is set when all bits of the result are s The V bit is used to indicate if a twos-complement overflow has occurred as a result of the operation. The bit is normally used to indicate if a carry from an aition or a borrow has occurred as a result of a subtraction. The bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate with and through the carry bit to facilitate multiple-word shift operations. The STOP disable (S) bit is used to allow or disallow the STOP instruction. The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable interrupt sources. The XIRQ mask (X bit) is used to disable interrupts from the XIRQ pin.

2 Table - Instruction Set (Sheet 1 of ) Mnemonic Operation Description ressing Instruction ondition odes Mode Opcode Operand ycles S X H I N Z V + INH 1 s X to X IX + ( : ) IX INH Y to Y IY + ( : ) IY INH 18 D (opr) with arry + M + 89 to D (opr) with arry + M + 9 to D9 F9 E9 18 E9 DD (opr) Memory + M 8 to 9 18 DD (opr) Memory + M to D F E 18 E DDD (opr) 1-it to D D + (M : M + 1) D D F E 18 E ND (opr) ND (opr) SL (opr) SL SL SLD SR ND with Memory ND with Memory rithmetic Shift Left rithmetic Shift Left rithmetic Shift Left rithmetic Shift Left D rithmetic Shift Right M M D F E 18 E 8 8 b b 18 8 INH 8 b b b b b b b b INH 8 INH 18 b b SR rithmetic Shift Right INH b b SR rithmetic Shift Right INH b b (rel) ranch if arry? = REL rr lear LR (opr) (msk) lear it(s) M (mm) M 1 1D mm mm 18 1D mm 8 S (rel) ranch if arry? = 1 REL rr Set EQ (rel) ranch if =? Z = 1 REL rr GE (rel) ranch if? N V = REL rr M8H11F1 ENTRL PROESSING UNIT MOTOROL TEHNIL DT -9

3 Mnemonic Operation Description ressing Instruction ondition odes Mode Opcode Operand ycles S X H I N Z V GT (rel) ranch if >? Z + (N V) = REL E rr HI (rel) ranch if? + Z = REL rr Higher HS (rel) ranch if? = REL rr Higher or Same IT (opr) it(s) Test M 8 with Memory 9 18 IT (opr) it(s) Test M with Memory D F E 18 E LE (rel) ranch if? Z + (N V) = 1 REL F rr LO (rel) ranch if? = 1 REL rr Lower LS (rel) ranch if? + Z = 1 REL rr Lower or Same LT (rel) ranch if <? N V = 1 REL D rr MI (rel) ranch if? N = 1 REL rr Minus NE (rel) ranch if not =? Z = REL rr PL (rel) ranch if Plus? N = REL rr R (rel) ranch lways? 1 = 1 REL rr RLR(opr) (msk) ranch if it(s) lear? M mm = 1 1F mm rr mm rr (rel) 18 1F mm rr 8 RN (rel) ranch Never? 1 = REL 1 rr RSET(opr) (msk) (rel) SET (opr) (msk) SR (rel) ranch if it(s) Set? (M) mm = Set it(s) M + mm M ranch to Subroutine ranch if 1 1E 18 1E mm rr mm rr mm rr mm mm mm 8 8 See Figure REL 8D rr V (rel)? V = REL 8 rr Overflow lear VS (rel) ranch if? V = 1 REL 9 rr Overflow Set ompare to INH 11 L lear arry it INH LI lear Interrupt I INH E Mask LR (opr) lear Memory M F 1 yte F LR LR LV MP (opr) MP (opr) lear lear lear Overflow Flag ompare to Memory ompare to Memory Table - Instruction Set (Sheet of ) 18 F INH F 1 INH F 1 V INH M M D1 F1 E1 18 E1 MOTOROL ENTRL PROESSING UNIT M8H11F1-1 TEHNIL DT

4 OM (opr) OM OM PD (opr) PX (opr) PY (opr) D DE (opr) DE DE DES DEX DEY EOR (opr) EOR (opr) FDIV IDIV IN (opr) IN IN INS INX Ones omplement Memory yte Ones omplement Ones omplement ompare D to Memory 1-it ompare X to Memory 1-it ompare Y to Memory 1-it Decimal djust Memory yte Index Register X Index Register Y Exclusive OR with Memory Exclusive OR with Memory Fractional Divide 1 by 1 Integer Divide 1 by 1 Memory yte Index Register X Table - Instruction Set (Sheet of ) Mnemonic Operation Description ressing Instruction ondition odes Mode Opcode Operand ycles S X H I N Z V $FF M M 1 18 $FF INH 1 $FF INH 1 D M : M + 1 IX M : M D 8 9 D IY M : M djust Sum to D INH 19 M 1 M 18 1 INH 1 INH SP 1 SP INH IX 1 IX INH 9 IY 1 IY INH 18 9 M M 8 D8 F8 E8 18 E8 D / IX IX; r D INH 1 D / IX IX; r D INH 1 M + 1 M INH + 1 INH SP + 1 SP INH 1 IX + 1 IX INH 8 M8H11F1 ENTRL PROESSING UNIT MOTOROL TEHNIL DT -11

5 Mnemonic Operation Description ressing Instruction ondition odes Mode Opcode Operand ycles S X H I N Z V IY + 1 IY INH 18 8 INY Index Register Y JMP (opr) Jump See Figure JSR (opr) LD (opr) LD (opr) LDD (opr) LDS (opr) LDX (opr) LDY (opr) LSL (opr) LSL LSL LSLD LSR (opr) Jump to Subroutine Load Load Load Double D Load Stack Pointer Load Index Register X Load Index Register Y Left Left Left Left Double Right See Figure M M M,M + 1 M : M + 1 SP M : M + 1 IX M : M + 1 IY b b b b Table - Instruction Set (Sheet of ) b b b b b b b b E E 18 E 9D D D 18 D D F E 18 E D F E 18 E 8E 9E E E 18 E E DE FE EE D EE 18 E 18 DE 18 FE 1 EE 18 EE INH 8 INH 8 INH 18 LSR INH Right b b LSR INH Right b b LSRD Right Double INH b b b b MUL Multiply 8 by 8 D INH D 1 NEG (opr) Two s omplement M M Memory yte 18 NEG Two s INH omplement NEG Two s omplement INH MOTOROL ENTRL PROESSING UNIT M8H11F1-1 TEHNIL DT

6 Mnemonic Operation Description ressing Instruction ondition odes Mode Opcode Operand ycles S X H I N Z V NOP No operation No Operation INH 1 OR (opr) OR + M 8 9 (Inclusive) 18 OR (opr) OR + M D (Inclusive) F E 18 E PSH Push onto Stk,SP = SP 1 INH Stack PSH Push onto Stk,SP = SP 1 INH Stack PSHX Push X onto IX Stk,SP = SP INH Stack (Lo First) PSHY Push Y onto IY Stk,SP = SP INH 18 Stack (Lo First) PUL Pull from SP = SP + 1, Stk INH Stack PUL Pull from SP = SP + 1, Stk INH Stack PULX Pull X From Stack (Hi First) SP = SP +, IX Stk INH 8 PULY Pull Y from Stack (Hi First) Table - Instruction Set (Sheet of ) SP = SP +, IY Stk INH 18 8 ROL (opr) Rotate Left 9 9 b b 18 9 ROL Rotate Left INH 9 b b ROL Rotate Left INH 9 b b ROR (opr) Rotate Right b b 18 ROR Rotate Right INH b b ROR Rotate Right INH b b RTI Return from See Figure INH 1 Interrupt RTS Return from See Figure INH 9 Subroutine S Subtract from INH 1 S (opr) Subtract with M 8 arry from 9 18 S (opr) Subtract with M arry from D F E 18 E SE Set arry 1 INH D 1 SEI Set Interrupt 1 I INH F 1 Mask SEV Set Overflow Flag 1 V INH 1 ST (opr) Store M 9 18 M8H11F1 ENTRL PROESSING UNIT MOTOROL TEHNIL DT -1

7 Mnemonic Operation Description ressing Instruction ondition odes Mode Opcode Operand ycles S X H I N Z V ST (opr) Store M D F E 18 E STD (opr) Store D M, M + 1 DD FD ED 18 ED STOP Stop Internal INH F locks STS (opr) Store Stack Pointer SP M : M + 1 STX (opr) STY (opr) SU (opr) SU (opr) SUD (opr) Store Index Register X Store Index Register Y Subtract Memory from Subtract Memory from Subtract Memory from D IX M : M + 1 IY M : M + 1 M M D M : M + 1 D 9F F F 18 F DF FF EF D EF 18 DF 18 FF 1 EF 18 EF D F E 18 E See Figure INH F 1 1 SWI Software Interrupt T Transfer to INH 1 TP Transfer to R INH Register T Transfer to INH 1 TEST TEST (Only in ress us ounts INH * Test Modes) TP Transfer R INH Register to TST (opr) Test for M D or Minus D TST TST TSX TSY TXS TYS WI XGDX XGDY Table - Instruction Set (Sheet of ) 18 D Test for INH D or Minus Test for INH D or Minus Transfer SP + 1 IX INH to X Transfer SP + 1 IY INH 18 to Y Transfer X to IX 1 SP INH Transfer Y to IY 1 SP INH 18 Wait for Stack Regs & WIT INH E ** Interrupt Exchange D IX D, D IX INH 8F with X Exchange D IY D, D IY INH 18 8F with Y MOTOROL ENTRL PROESSING UNIT M8H11F1-1 TEHNIL DT

8 ycle * Infinity or until reset occurs ** 1 cycles are used beginning with the opcode fetch. wait state is entered which remains in eect for an integer number of MPU E-clock cycles (n) until an interrupt is recognized. Finally, two aitional cycles are used to fetch the appropriate interrupt vector (1 + n total). Operands = 8-bit direct aress ($ $FF) (high byte assumed to be $) = 8-bit positive oset $ () to $FF () (is aed to index) hh = High-order byte of 1-bit extended aress = One byte of immediate data jj = High-order byte of 1-bit immediate data kk = Low-order byte of 1-bit immediate data ll = Low-order byte of 1-bit extended aress mm = 8-bit mask (set bits to be aected) rr = Signed relative oset $8 ( 18) to $F (+1) (oset relative to aress following machine code oset byte)) Operators ( ) ontents of register shown inside parentheses Is transferred to Is pulled from stack Is pushed onto stack oolean ND + rithmetic aition symbol except where used as inclusive- OR symbol in oolean formula Exclusive-OR * Multiply : oncatenation rithmetic subtraction symbol or negation symbol (two s complement) ondition odes it not changed it always cleared 1 it always set it cleared or set, depending on operation it can be cleared, cannot become set

Table 1: Mnemonics Operations Dictionary. Add Accumulators Add B to Y. Add with carry to B. Add Memory to B. Add 16-bit to D And B with Memory

Table 1: Mnemonics Operations Dictionary. Add Accumulators Add B to Y. Add with carry to B. Add Memory to B. Add 16-bit to D And B with Memory Table 1: Mnemonics s Dictionary ABA ABX ABY ADCA ADCB ADDA ADDB ADDD ANDA ANDB ASL ASLA ASLB ASLD ASR ASRA ASRB BCC BCLR BCS BEQ BGE BGT BHI BHS BITA BITB BLE BLO BLS BLT Add Accumulators Add B to X Add