LC3DataPath ECE2893. Lecture 9a. ECE2893 LC3DataPath Spring / 14

Transcription

1 LC3DataPath ECE2893 Lecture 9a ECE2893 LC3DataPath Spring / 14

2 LC3 Data Path [4:0] FINITE MACHINE STATE MEMORY IR ADDR2MUX ADDR1MUX + GateMARMUX LDPC MARMUX ZEXT SEXT SEXT SEXT RESET GateALU +1 PCMUX GatePC PC FILE REGISTER SR2MUX SR2 OUT SR1 OUT SEXT MEMEN MEMRW ALUOP 0 LOGIC SR1 SR2 LDREG DR PCMUXSEL LDIR [5:0] [8:0] [10:0] [7:0] A2MSEL MARMUXSEL MDR GateMDR LDMAR MAR P Z N LDMDR2 LDMDR1 A1MSEL LDCC ALU ECE2893 LC3DataPath Spring / 14

3 The Register Component Outputs Clock Register Enable Inputs 1 A Register loads and retains the value specified by the Inputs ONLY IF 1 The Enable bit is a 1 (true) AND 2 The Clock transitions from a 1 to a 0 2 The value on the Output is the most recently loaded input, and does not change until a new value is loaded ECE2893 LC3DataPath Spring / 14

4 The Register File Component SR1 Out SR2 Out Clock Register File LDREG SR1 SR2 Inputs DR A Register File is nothing more than a collection of registers In the case of LC3, it is 8 registers 2 Since we must address 8 register, we need a 3 bit Destination Register to specify which register is to be loaded 3 Also, we need to allow two different registers output at the same time For example, thing about the ADD R0,R1,R2 instruction Both R1 and R2 are needed at the same time Thus we have 2 -bit outs, SR1 Out and SR2 Out and two 3 bit selectors SR1 and SR2 1 ECE2893 LC3DataPath Spring / 14

5 The Multiplexer File Component Output Selector 2 Multiplexer I0 I1 I2 I3 1 A Multiplexer has k inputs (k is four in the above example) and a single output 2 The output is a copy of one of the k inputs, determined by the value in the Selector 3 For example, if the Selector is the value 1, then the output is equal to input 1 4 There is no clock or enable The output is always one of the inputs ECE2893 LC3DataPath Spring / 14

6 The Arithmetic/Logical Unit Component Input 1 Input 2 ALUOP 2 ALU Output 1 The ALU produces an output that is some arithmetic or logical combination of the two inputs 2 ALUOP controls the exact operation to be performed For the LC3, the values are: 1 0 = ADD 2 1 = Logical AND 3 2 = Logical NOT 4 3 = No Operation, output is just the Input 1 unmodified ECE2893 LC3DataPath Spring / 14

7 The Sign Extender Component Sign Extend k 1 A sign extender takes a k bit input, and produces a bit output 2 The upper bit (the 2 k 1 bit) of the input is replicated to bits 2 k through 2 15 of the output 3 The LC3 design uses several different sign extenders, with k = 5, 6, 9 and 11 ECE2893 LC3DataPath Spring / 14

8 The Zero Extender Component Zero Extend k 1 A zero extender takes a k bit input, and produces a bit output 2 Bits 2 k through 2 15 of the output are set to zero 3 The LC3 design uses a single zero extender, with k = 8 ECE2893 LC3DataPath Spring / 14

9 The Memory Component MDR Out MDR In Memory 65,536 words bits each Enable Read/Write MAR 1 The LC3 memory consists of 65,536 (2 ) words of bits each 2 The Memory Address Register (MAR) input specifies which address is to be read or written 3 The Enable input (a single bit) specifies the memory should do something (Enable = 1) or not Enable = 0 4 If enabled, the Read/Write input determines if the operation is a read Read/Write = 1 or write Read/Write = 0 5 The Memory Data Register Input (MDR In) is the data to be written to memory if enabled and Read/Write = 0 6 The Memory Data Register Output (MDR Out) is the contents of the memory location that was read, if enabled and Read/Write = 1 ECE2893 LC3DataPath Spring / 14

10 The Tri State Bus Component In1 In2 In3 Output Output Enable 1 Enable 2 Enable 3 1 The Tri State Bus has multiple inputs and multiple outputs 2 At any point in time, only a SINGLE input can be enabled 3 At any point in time, ALL outputs are a copy of the single enabled input ECE2893 LC3DataPath Spring / 14

11 The Finite State Machine Component IR Reset Finite State Machine NZP ALUOp LDPC Lots more 1 The Finite State Machine controls all enables and multiplexer inputs that allow the LC3 to execute the instructions 2 There are three inputs: 1 Instruction Register Input 2 NZP Input 3 Reset Input 3 There are 49 output control signals ECE2893 LC3DataPath Spring / 14

12 Executing Instructions 1 Like all CPU s, the LC3 executes instructions one at a time 2 Also like all CPU s the LC3 goes through several well-defined steps for each instruction 3 These smaller steps used in instruction execution are sometimes called micro-operations, or micro-ops 4 For the LC3, the possible states for each instruction are: 1 Fetch - Read memory and fetch the next instruction 2 Decode - Determine the instruction opcode 3 Address Evaluation - Determine the effective address of the operand 4 Operand Fetch - Read the operand frommemory 5 Execute - Perform the needed arithmetic or logical operation 6 Store Result - Store the computed result in the correc location 5 Clearly, not all instructions go through exactly all the states listed above ECE2893 LC3DataPath Spring / 14

13 Sample Instruction Execution 1 Initially, the LC3 is in Fetch state 2 To fetch an instruction, the following control signals are needed: 1 PCMUXSel = 2 (select the PC+1 input) 2 LdPC = 1 (Load a new PC value on next tick) 3 GatePC = 1 (Load the current PC value on the bus) 4 LDMAR = 1 (Load the PC value into the memory address register) 3 The above cause the current PC to be loaded into MAR, and the PC to advance to PC On the next clock tick: 1 MEMEN = 1 (enable memory) 2 MEMRW = 0 (read memory) 3 LDMDR1 (store the read value in the MDR This is the next instruction 5 On the next clock tick: 1 LdPC = 0 (remove PC from bus) 2 GateMDR = 1 (Place instruction value on the bus) 3 LDIR = 1 (Load instruction into the IR register) 6 At this point the instruction FETCH micro-ops have completed ECE2893 LC3DataPath Spring / 14

14 Sample Instruction Execution 1 Next the DECODE state, which determines the value for several signals, depending on the type of instruction (opcode) 1 Source Register 1, Source Register 2 (or immediate value) 2 Destination register 3 Base register 4 PC Offset 9 value 5 NZP value 2 Depending on the instruction, the above values are determined by the finite state machine, and appropriate control signals enabled 3 Again, depending on the opcode, the state progresses through the remaing other states, such as EVALUATE ADDRESS, OPERAND FETCH, EXECUTE, and STORE RESULT ECE2893 LC3DataPath Spring / 14