CS152 Computer Architecture and Engineering Lecture 15

Transcription

1 CS152 Computer Architecture and Engineering Lecture 15 Advanced pipelining/compiler Scheduling Dynamic Scheduling I March 13, 2001 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: Review: Pipelining Hazards limit performance Structural: need more HW resources Data: need forwarding, compiler scheduling Control: early evaluation & PC, delayed branch, prediction Data hazards must be handled carefully: RAW data hazards handled by forwarding WAW and WAR hazards don t exist in 5-stage pipeline MIPS I instruction set architecture made pipeline visible (delayed branch, delayed load) Exceptions in 5-stage pipeline recorded when they occur, but acted on only at WB (end of MEM) stage Must flush all later instructions (at earlier pipe stages) More performance from deeper pipelines, parallelism? Lec15.1 Lec15.2 Review: Resolve RAW by forwarding (or bypassing) Question: Critical Path??? Regs Forward mux B alu S D mem m IAU npc I mem op rw rs rt A im n op rw n op n op PC Regs rw rw Detect nearest valid write op operand register and forward into op latches, bypassing remainder of the pipe Increase muxes to add paths from pipeline registers Data Forwarding = Data Bypassing Lec15.3 Regs Forward mux B alu S D mem m A im PC Sel Equal Regs Bypass path is invariably trouble Options? Make logic really fast Move forwarding after muxes» Problem: screws up branches that require forwarding!» Use same tricks as carry-skip adder to fix this?» This option may just push delay around.! Insert an extra cycle for branches that need forwarding?» Or: hit common case of forwarding from EX stage and stall for forward from memory? Lec15.4

2 Recap: Data Hazards I-Fet ch DCD MemOpFetch OpFetch Exec Store Structural Hazard IFetch DCD I-Fet ch DCD OpFetch Jump Control Hazard Recap: Data Stationary Control The Main Control generates the control signals during Reg/Dec Control signals for Exec (ExtOp, ALUSrc,...) are used 1 cycle later Control signals for Mem (MemWr Branch) are used 2 cycles later Control signals for Wr (MemtoReg MemWr) are used 3 cycles later Reg/Dec Exec Mem Wr IF DCD EX Mem WB IFetch DCD IF DCD EX Mem WB IF DCD EX Mem WB IF DCD OF RAW (read after write) Data Hazard IF DCD OF Ex RS WAW Data Hazard (write after write) Ex Mem WAR Data Hazard (write after read) Lec15.5 IF/ID Register Main Control ExtOp ALUSrc ALUOp RegDst MemW Branch r MemtoReg RegWr ID/Ex Register ExtOp ALUSrc ALUOp RegDst MemW Branch r MemtoReg RegWr Ex/Mem Register MemW rbranch MemtoReg RegWr Mem/Wr Register MemtoReg RegWr Lec15.6 Review: The exception problem in simple pipeline Time Data TLB Bad Inst Inst TLB fault Overflow Program Flow IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB Use pipeline to sort this out! Pass exception status along with instruction. Keep track of PCs for every instruction in pipeline. Don t act on exception until it reache WB stage Handle interrupts through faulting noop in IF stage When instruction reaches WB stage: Save PC Ÿ EPC, Interrupt vector addr Ÿ PC Turn all instructions in earlier stages into noops! IFetch Dcd Exec Mem WB Lec15.7 Resolution: Freeze above & Bubble Below Regs B alu S IAU npc I mem op rw rs rt A im n op rw n op PC D mem m n op rw Regs rw bubble freeze Flush accomplished by setting invalid bit in pipeline Lec15.8

3 FYI: MIPS R3000 clocking discipline MIPS R3000 Instruction Pipeline phi1 phi2 2-phase non-overlapping clocks Pipeline stage is two (level sensitive) latches Inst Fetch Decode Reg. Read ALU / E.A Memory Write Reg TLB I-Cache RF Operation WB Resource Usage E.A. TLB D-Cache TLB TLB I-cache RF WB Edge-triggered phi1 phi2 phi1 ALUALU D-Cache Write in phase 1, read in phase 2 => eliminates bypass from WB Lec15.9 Lec15.10 Recall: Data Hazard on r1 MIPS R3000 Multicycle Operations I n s t r. O r d e r Time (clock cycles) IF ID/RF EX MEM WB add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 ALU Im Reg Dm Reg ALU Im Reg Dm Reg ALU Im Reg Dm Reg Im ALU Reg Dm Reg ALU Im Reg Dm Reg With MIPS R3000 pipeline, no need to forward from WB stage Lec15.11 op Rd Ra Rb mul Rd Ra Rb Rd Rd to reg file Ex: Multiply, Divide, Cache Miss A R T B Use control word of local stage to step through multicycle operation Stall all stages above multicycle operation in the pipeline Drain (bubble) stages below it Alternatively, launch multiply/divide to autonomous unit, only stall pipe if attempt to get result before ready - This means stall mflo/mfhi in decode stage if multiply/divide still executing - Extra credit in Lab 5 does this Lec15.12

4 Is CPI = 1 for our pipeline? Remember that CPI is an Average # cycles/inst IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB CPI here is 1, since the average throughput is 1 instruction every cycle. What if there are stalls or multi-cycle execution? Usually CPI > 1. How close can we get to 1?? Recall: Compute CPI? Start with Base CPI Add stalls CPI CPI stall CPI base STALL CPI stall u freq STALL u freq type1 type1 type2 type2 Suppose: CPI base =1 Freq branch =20%, freq load =30% Suppose branches always cause 1 cycle stall Loads cause a 100 cycle stall 1% of time Then: CPI = 1 + (1u0.20)+(100 u 0.30u0.01)=1.5 Multicycle? Could treat as: CPI stall =(CYCLES-CPI base ) u freq inst Lec15.13 Lec15.14 Case Study: MIPS R4000 (200 MHz) Case Study: MIPS R Stage Pipeline: IF first half of fetching of instruction; PC selection happens here as well as initiation of instruction cache access. IS second half of access to instruction cache. RF instruction decode and register fetch, hazard checking and also instruction cache hit detection. EX execution, which includes effective address calculation, ALU operation, and branch target computation and condition evaluation. DF data fetch, first half of access to data cache. DS second half of access to data cache. TC tag check, determine whether the data cache access hit. WB write back for loads and register-register operations. 8 Stages: What is impact on Load delay? Branch delay? Why? 7:2&\FOH /RDG/DWHQF\ 7+5((&\FOH %UDQFK/DWHQF\ FRQGLWLRQVHYDOXDWHG GXULQJSKDVH 'HOD\VORWSOXVWZRVWDOOV %UDQFKOLNHO\FDQFHOVGHOD\VORWLIQRWWDNHQ ') ') '6 ') '6 ') 7& '6 ') 7& '6 ') :% 7& '6 ') :% 7& '6 ') Lec15.15 Lec15.16

5 MIPS R4000 Floating Point FP Adder, FP Multiplier, FP Divider Last step of FP Multiplier/Divider uses FP Adder HW 8 kinds of stages in FP units: Stage Functional unit Description A FP adder Mantissa ADD stage D FP divider Divide pipeline stage E FP multiplier Exception test stage M FP multiplier First stage of multiplier N FP multiplier Second stage of multiplier R FP adder Rounding stage S FP adder Operand shift stage U Unpack FP numbers MIPS FP Pipe Stages FP Instr Add, Subtract U S+A A+R R+S Multiply U E+M M M M N N+A R Divide U A R D 28 D+A D+R, D+R, D+A, D+R, A, R Square root U E (A+R) 108 A R Negate U S Absolute value U S FP compare U A R Stages: M First stage of multiplier N Second stage of multiplier A Mantissa ADD stage R Rounding stage D Divide pipeline stage S Operand shift stage E Exception test stage U Unpack FP numbers Lec15.17 Lec15.18 R4000 Performance Administrivia t ideal CPI of 1: FP structural stalls: t enough FP hardware (parallelism) FP result stalls: RAW data hazard (latency) Branch stalls (2 cycles + unfilled slots) Load stalls (1 or 2 clock cycles) eqntott espresso gcc li doduc nasa7 ora spice2g6 su2cor tomcatv Remember: Sections in 119 Cory tomorrow! You will demonstrate your Lab 4 processors Get moving on Lab 5! This lab is even harder than Lab4. Trickier to debug! Start with unpipelined version?» Interesting thought May or may not help Dynamic scheduling techniques discussed in the Other Hennessy & Patterson book: Computer Architecture: A Quantitative Approach Chapter 4 Base Load stalls Branch stalls FP result stalls FP structural stalls Lec15.19 Lec15.20

6 Can we somehow make CPI closer to 1? Let s assume full pipelining: If we have a 4-cycle instruction, then we need 3 instructions between a producing instruction and its use: multf $F0,$F2,$F4 delay-1 delay-2 delay-3 addf $F6,$F10,$F0 (DUOLHVWIRUZDUGLQJIRU F\FOHLQVWUXFWLRQV (DUOLHVWIRUZDUGLQJIRU F\FOHLQVWUXFWLRQV )HWFK 'HFRGH ([ ([ ([ ([ :% FP Loop: Where are the Hazards? Loop: LD F0,0(R1) ;F0=vector element ADDD F4,F0,F2 ;add scalar from F2 SD 0(R1),F4 ;store result SUBI R1,R1,8 ;decrement pointer 8B (DW) BNEZ R1,Loop ;branch R1!=zero NOP ;delayed branch slot,qvwuxfwlrq,qvwuxfwlrq /DWHQF\LQ SURGXFLQJUHVXOW XVLQJUHVXOW FORFNF\FOHV )3$/8RS $QRWKHU)3$/8RS )3$/8RS 6WRUHGRXEOH /RDGGRXEOH )3$/8RS /RDGGRXEOH 6WRUHGRXEOH,QWHJHURS,QWHJHURS DGGI GHOD\ GHOD\ GHOD\ PXOWI :KHUHDUHWKHVWDOOV" Lec15.21 Lec15.22 FP Loop Showing Stalls Revised FP Loop Minimizing Stalls 1 Loop: LD F0,0(R1) ;F0=vector element 2 stall 3 ADDD F4,F0,F2 ;add scalar in F2 4 stall 5 stall 6 SD 0(R1),F4 ;store result 7 SUBI R1,R1,8 ;decrement pointer 8B (DW) 8 BNEZ R1,Loop ;branch R1!=zero 9 stall ;delayed branch slot,qvwuxfwlrq,qvwuxfwlrq /DWHQF\LQ SURGXFLQJUHVXOW XVLQJUHVXOW FORFNF\FOHV )3$/8RS $QRWKHU)3$/8RS )3$/8RS 6WRUHGRXEOH /RDGGRXEOH )3$/8RS 9 clocks: Rewrite code to minimize stalls? Lec Loop: LD F0,0(R1) 2 stall 3 ADDD F4,F0,F2 4 SUBI R1,R1,8 5 BNEZ R1,Loop ;delayed branch 6 SD 8(R1),F4 ;altered when move past SUBI 6ZDS%1(=DQG6'E\FKDQJLQJDGGUHVVRI6',QVWUXFWLRQ,QVWUXFWLRQ /DWHQF\LQ SURGXFLQJUHVXOW XVLQJUHVXOW FORFNF\FOHV )3$/8RS $QRWKHU)3$/8RS )3$/8RS 6WRUHGRXEOH /RDGGRXEOH )3$/8RS 6 clocks: Unroll loop 4 times code to make faster? Lec15.24

7 Unroll Loop Four Times (straightforward way) 1 Loop:LD F0,0(R1) F\FOHVWDOO 2 ADDD F4,F0,F2 F\FOHVVWDOO 3 SD 0(R1),F4 ;drop SUBI & BNEZ 4 LD F6,-8(R1) 5 ADDD F8,F6,F2 6 SD -8(R1),F8 ;drop SUBI & BNEZ 7 LD F10,-16(R1) 8 ADDD F12,F10,F2 9 SD -16(R1),F12 ;drop SUBI & BNEZ 10 LD F14,-24(R1) 11 ADDD F16,F14,F2 12 SD -24(R1),F16 13 SUBI R1,R1,#32 ;alter to 4*8 14 BNEZ R1,LOOP 15 NOP Rewrite loop to minimize stalls? [ FORFNF\FOHVRUSHULWHUDWLRQ $VVXPHV5LVPXOWLSOHRI Unrolled Loop That Minimizes Stalls 1 Loop:LD F0,0(R1) 2 LD F6,-8(R1) 3 LD F10,-16(R1) 4 LD F14,-24(R1) 5 ADDD F4,F0,F2 6 ADDD F8,F6,F2 7 ADDD F12,F10,F2 8 ADDD F16,F14,F2 9 SD 0(R1),F4 10 SD -8(R1),F8 11 SD -16(R1),F12 12 SUBI R1,R1,#32 13 BNEZ R1,LOOP 14 SD 8(R1),F16 ; 8-32 = -24 FORFNF\FOHVRUSHULWHUDWLRQ :KHQVDIHWRPRYHLQVWUXFWLRQV" What assumptions made when moved code? OK to move store past SUBI even though changes register OK to move loads before stores: get right data? When is it safe for compiler to do such changes? Lec15.25 Lec15.26 Getting CPI < 1: Issuing Multiple Instructions/Cycle Getting CPI < 1: Issuing Multiple Instructions/Cycle Two main variations: Superscalar and VLIW Superscalar: varying no. instructions/cycle (1 to 6) Parallelism and dependencies determined/resolved by HW IBM PowerPC 604, Sun UltraSparc, DEC Alpha 21164, HP 7100 Very Long Instruction Words (VLIW): fixed number of instructions (16) parallelism determined by compiler Pipeline is exposed; compiler must schedule delays to get right result Explicit Parallel Instruction Computer (EPIC)/ Intel 128 bit packets containing 3 instructions (can execute sequentially) Can link 128 bit packets together to allow more parallelism Compiler determines parallelism, HW checks dependencies and fowards/stalls Superscalar DLX: 2 instructions, 1 FP & 1 anything else Fetch 64-bits/clock cycle; Int on left, FP on right Can only issue 2nd instruction if 1st instruction issues More ports for FP registers to do FP load & FP op in a pair Type PipeStages Int. instruction IF ID EX MEM WB FP instruction IF ID EX MEM WB Int. instruction IF ID EX MEM WB FP instruction IF ID EX MEM WB Int. instruction IF ID EX MEM WB FP instruction IF ID EX MEM WB 1 cycle load delay expands to 3 instructions in SS instruction in right half can t use it, nor instructions in next slot Lec15.27 Lec15.28

8 Loop Unrolling in Superscalar Integer instruction FP instruction Clock cycle Loop: LD F0,0(R1) 1 LD F6,-8(R1) 2 LD F10,-16(R1) ADDD F4,F0,F2 3 LD F14,-24(R1) ADDD F8,F6,F2 4 LD F18,-32(R1) ADDD F12,F10,F2 5 SD 0(R1),F4 ADDD F16,F14,F2 6 SD -8(R1),F8 ADDD F20,F18,F2 7 SD -16(R1),F12 8 SD -24(R1),F16 9 SUBI R1,R1,#40 10 BNEZ R1,LOOP 11 SD -32(R1),F20 12 Unrolled 5 times to avoid delays (+1 due to SS) 12 clocks, or 2.4 clocks per iteration Lec15.29 Limits of Superscalar While Integer/FP split is simple for the HW, get CPI of 0.5 only for programs with: Exactly 50% FP operations hazards If more instructions issue at same time, greater difficulty of decode and issue Even 2-scalar => examine 2 opcodes, 6 register specifiers, & decide if 1 or 2 instructions can issue VLIW: tradeoff instruction space for simple decoding The long instruction word has room for many operations By definition, all the operations the compiler puts in the long instruction word can execute in parallel E.g., 2 integer operations, 2 FP ops, 2 Memory refs, 1 branch» 16 to 24 bits per field => 7*16 or 112 bits to 7*24 or 168 bits wide Need compiling technique that schedules across several branches Lec15.30 Loop Unrolling in VLIW Software Pipelining Memory Memory FP FP Int. op/ Clock reference 1 reference 2 operation 1 op. 2 branch LD F0,0(R1) LD F6,-8(R1) 1 LD F10,-16(R1) LD F14,-24(R1) 2 LD F18,-32(R1) LD F22,-40(R1) ADDD F4, F0, F2 ADDD F8,F6,F2 3 LD F26,-48(R1) ADDD F12, F10, F2 ADDD F16,F14,F2 4 ADDD F20, F18, F2 ADDD F24,F22,F2 5 SD 0(R1),F4 SD -8(R1),F8 ADDD F28, F26, F2 6 SD -16(R1),F12 SD -24(R1),F16 7 SD -32(R1),F20 SD -40(R1),F24 SUBI R1,R1,#48 8 SD -0(R1),F28 BNEZ R1,LOOP 9 Unrolled 7 times to avoid delays 7 results in 9 clocks, or 1.3 clocks per iteration Need more registers in VLIW(EPIC => 128int + 128FP) Observation: if iterations from loops are independent, then can get more ILP by taking instructions from different iterations Software pipelining: reorganizes loops so that each iteration is made from instructions chosen from different iterations of the original loop (- Tomasulo in SW) Softwarepipelined iteration Iteration 0 Iteration 1 Iteration 2 Iteration 3 Iteration 4 Lec15.31 Lec15.32

9 Software Pipelining Example Before: Unrolled 3 times 1 LD F0,0(R1) 2 ADDD F4,F0,F2 3 SD 0(R1),F4 4 LD F6,-8(R1) 5 ADDD F8,F6,F2 6 SD -8(R1),F8 7 LD F10,-16(R1) 8 ADDD F12,F10,F2 9 SD -16(R1),F12 10 SUBI R1,R1,#24 11 BNEZ R1,LOOP After: Software Pipelined 1 SD 0(R1),F4 ; Stores M[i] 2 ADDD F4,F0,F2 ; Adds to M[i-1] 3 LD F0,-16(R1); Loads M[i-2] 4 SUBI R1,R1,#8 5 BNEZ R1,LOOP overlapped ops Symbolic Loop Unrolling Maximize result-use distance Less code space than unrolling Fill & drain pipe only once per loop vs. once per each unrolled iteration in loop unrolling SW Pipeline Time Loop Unrolled Time Software Pipelining with Loop Unrolling in VLIW Memory Memory FP FP Int. op/ Clock reference 1 reference 2 operation 1 op. 2 branch LD F0,-48(R1) ST 0(R1),F4 ADDD F4,F0,F2 1 LD F6,-56(R1) ST -8(R1),F8 ADDD F8,F6,F2 SUBI R1,R1,#24 2 LD F10,-40(R1) ST 8(R1),F12 ADDD F12,F10,F2 BNEZ R1,LOOP 3 Software pipelined across 9 iterations of original loop In each iteration of above loop, we:» Store to m,m-8,m-16 (iterations I-3,I-2,I-1)» Compute for m-24,m-32,m-40 (iterations I,I+1,I+2)» Load from m-48,m-56,m-64 (iterations I+3,I+4,I+ 9 results in 9 cycles, or 1 clock per iteration Average: 3.3 ops per clock, 66% efficiency te: Need less registers for software pipelining (only using 7 registers here, was using 1 Lec15.33 Lec15.34 Can we use HW to get CPI closer to 1? Problems? Why in HW at run time? Works when can t know real dependence at compile time Compiler simpler Code for one machine runs well on another Key idea: Allow instructions behind stall to proceed: DIVD F0,F2,F4 ADDD F10,F0,F8 SUBD F12,F8,F14 Out-of-order execution => out-of-order completion. Disadvantages? Complexity Precise interrupts harder! (Talk about this next time) How do we prevent WAR and WAW hazards? How do we deal with variable latency? Forwarding for RAW hazards harder. &ORFN&\FOH1XPEHU,QVWUXFWLRQ /' )5,' 0(0 :% /' )5,' 0(0 :% 08/7' ))),' VWDOO (0 :% 68%' ))),' $ $ 0(0 :% ',9' ))),' VWDOO VWDOO VWDOO VWDOO VWDOO VWDOO VWDOO VWDOO VWDOO ' ' $''' ))),' $ $ 0(0 :% :$5 5$: Lec15.35 Lec15.36

10 Scoreboard: a bookkeeping technique Scoreboard Architecture(CDC 6600) Out-of-order execution divides ID stage: 1. Issue decode instructions, check for structural hazards 2. Read operands wait until no data hazards, then read operands Scoreboards date to CDC6600 in 1963 Instructions execute whenever not dependent on previous instructions and no hazards. CDC 6600: In order issue, out-of-order execution, outof-order commit (or completion) forwarding! Imprecise interrupt/exception model for now 5HJLVWHUV )30XOW )30XOW )3'LYLGH )3$GG,QWHJHU )XQFWLRQDO8QLWV 6&25(%2$5' 0HPRU\ Lec15.37 Lec15.38 Scoreboard Implications Four Stages of Scoreboard Control Out-of-order completion => WAR, WAW hazards? Solutions for WAR: Stall writeback until registers have been read Read registers only during Read Operands stage Solution for WAW: Detect hazard and stall issue of new instruction until other instruction completes register renaming! Need to have multiple instructions in execution phase => multiple execution units or pipelined execution units Scoreboard keeps track of dependencies between instructions that have already issued. Scoreboard replaces ID, EX, WB with 4 stages Issue decode instructions & check for structural hazards (ID1) Instructions issued in program order (for hazard checking) Don t issue if structural hazard Don t issue if instruction is output dependent on any previously issued but uncompleted instruction (no WAW hazards) Read operands wait until no data hazards, then read operands (ID2) All real dependencies (RAW hazards) resolved in this stage, since we wait for instructions to write back data. forwarding of data in this model! Lec15.39 Lec15.40

11 Four Stages of Scoreboard Control Execution operate on operands (EX) The functional unit begins execution upon receiving operands. When the result is ready, it notifies the scoreboard that it has completed execution. Write result finish execution (WB) Stall until no WAR hazards with previous instructions: Example: DIVD F0,F2,F4 ADDD F10,F0,F8 SUBD F8,F8,F14 CDC 6600 scoreboard would stall SUBD until ADDD reads operands Three Parts of the Scoreboard Instruction status: Which of 4 steps the instruction is in Functional unit status: Indicates the state of the functional unit (FU). 9 fields for each functional unit Busy: Indicates whether the unit is busy or not Op: Operation to perform in the unit (e.g., + or ) Fi: Destination register Fj,Fk: Source-register numbers Qj,Qk: Functional units producing source registers Fj, Fk Rj,Rk: Flags indicating when Fj, Fk are ready Register result status Indicates which functional unit will write each register, if one exists. Blank when no pending instructions will write that register Lec15.41 Lec15.42 Scoreboard Example LD F6 34+ R2 LD F2 45+ R3 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 Integer Mult1 Mult2 Add Divide FU Detailed Scoreboard Pipeline Control,QVWUXFWLRQ VWDWXV,VVXH 5HDG RSHUDQGV ([HFXWLRQ FRPSOHWH :ULWH UHVXOW :DLWXQWLO 1RWEXV\)8 DQGQRWUHVXOW' 5M DQG5N )XQFWLRQDOXQLW GRQH %RRNNHHSLQJ %XV\)8 \HV2S)8 RS )L)8 C' )M)8 C6 )N)8 C6 4M 5HVXOW 6 4N 5HVXOWC6 5M QRW4M 5N QRW4N5HVXOW ' )8 5M 1R5N 1R I)MI )L)8 ILI4MI )8WKHQ5MI <HV RU5MI 1R ILI4NI )8WKHQ5MI <HV )NI )L)8RU 5HVXOW)L)8 %XV\)8 1R 5NI 1R Lec15.43 Lec15.44

12 Scoreboard Example: Cycle 1 LD F6 34+ R2 1 LD F2 45+ R3 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 Integer Yes Load F6 R2 Yes Mult1 Add Divide 1 FU Integer Scoreboard Example: Cycle 2 LD F6 34+ R2 1 2 LD F2 45+ R3 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 Integer Yes Load F6 R2 Yes Mult1 Add Divide 2 FU Integer Lec15.45,VVXHQG/'" Lec15.46 Scoreboard Example: Cycle 3 Scoreboard Example: Cycle 4 LD F6 34+ R LD F2 45+ R3 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 LD F2 45+ R3 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 Integer Yes Load F6 R2 Mult1 Add Divide 3 FU Integer Integer Mult1 Mult2 Add Divide 4 FU Integer,VVXH08/7" Lec15.47 Lec15.48

13 Scoreboard Example: Cycle 5 LD F2 45+ R3 5 MULTD F0 F2 F4 SUBD F8 F6 F2 DIVD F10 F0 F6 Integer Yes Load F2 R3 Yes Mult1 Add Divide 5 FU Integer Scoreboard Example: Cycle 6 LD F2 45+ R3 5 6 MULTD F0 F2 F4 6 SUBD F8 F6 F2 DIVD F10 F0 F6 Integer Yes Load F2 R3 Yes Mult1 Yes Mult F0 F2 F4 Integer Yes Add Divide 6 FU Mult1 Integer Lec15.49 Lec15.50 Scoreboard Example: Cycle 7 LD F2 45+ R MULTD F0 F2 F4 6 SUBD F8 F6 F2 7 DIVD F10 F0 F6 Integer Yes Load F2 R3 Mult1 Yes Mult F0 F2 F4 Integer Yes Add Yes Sub F8 F6 F2 Integer Yes Divide 7 FU Mult1 Integer Add Scoreboard Example: Cycle 8a (First half of clock cycle) LD F2 45+ R MULTD F0 F2 F4 6 SUBD F8 F6 F2 7 Integer Yes Load F2 R3 Mult1 Yes Mult F0 F2 F4 Integer Yes Add Yes Sub F8 F6 F2 Integer Yes Divide Yes Div F10 F0 F6 Mult1 Yes 8 FU Mult1 Integer Add Divide 5HDGPXOWLSO\RSHUDQGV" Lec15.51 Lec15.52

14 Scoreboard Example: Cycle 8b (Second half of clock cycle) MULTD F0 F2 F4 6 SUBD F8 F6 F2 7 Integer Mult1 Yes Mult F0 F2 F4 Yes Yes Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 8 FU Mult1 Add Divide Scoreboard Example: Cycle 9 SUBD F8 F6 F RWH 5HPDLQLQJ Integer 10 Mult1 Yes Mult F0 F2 F4 Yes Yes 2Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 9 FU Mult1 Add Divide Lec HDGRSHUDQGVIRU08/7 68%",VVXH$'''" Lec15.54 Scoreboard Example: Cycle 10 SUBD F8 F6 F2 7 9 Scoreboard Example: Cycle 11 SUBD F8 F6 F Integer 9Mult1 Yes Mult F0 F2 F4 1Add Yes Sub F8 F6 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 10 FU Mult1 Add Divide Integer 8Mult1 Yes Mult F0 F2 F4 0Add Yes Sub F8 F6 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 11 FU Mult1 Add Divide Lec15.55 Lec15.56

15 Scoreboard Example: Cycle 12 Integer 7Mult1 Yes Mult F0 F2 F4 Add Divide Yes Div F10 F0 F6 Mult1 Yes 12 FU Mult1 Divide Scoreboard Example: Cycle Integer 6Mult1 Yes Mult F0 F2 F4 Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 13 FU Mult1 Add Divide 5HDGRSHUDQGVIRU',9'" Lec15.57 Lec15.58 Scoreboard Example: Cycle 14 Scoreboard Example: Cycle Integer 5Mult1 Yes Mult F0 F2 F4 2 Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 Yes 14 FU Mult1 Add Divide Integer 4Mult1 Yes Mult F0 F2 F4 1 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 15 FU Mult1 Add Divide Lec15.59 Lec15.60

16 Scoreboard Example: Cycle Scoreboard Example: Cycle :$5+D]DUG Integer 3Mult1 Yes Mult F0 F2 F4 0 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 16 FU Mult1 Add Divide Integer 2Mult1 Yes Mult F0 F2 F4 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 17 FU Mult1 Add Divide Lec15.61 :K\QRWZULWHUHVXOWRI$''""" Lec15.62 Scoreboard Example: Cycle 18 Scoreboard Example: Cycle Integer 1Mult1 Yes Mult F0 F2 F4 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 18 FU Mult1 Add Divide Integer 0Mult1 Yes Mult F0 F2 F4 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Mult1 Yes 19 FU Mult1 Add Divide Lec15.63 Lec15.64

17 Scoreboard Example: Cycle Integer Mult1 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Yes Yes 20 FU Add Divide Scoreboard Example: Cycle Integer Mult1 Add Yes Add F6 F8 F2 Divide Yes Div F10 F0 F6 Yes Yes 21 FU Add Divide Lec15.65 :$5+D]DUGLVQRZJRQH Lec15.66 Scoreboard Example: Cycle Integer Mult1 Add 39 Divide Yes Div F10 F0 F6 22 FU Divide Faster than light computation (skip a couple of cycles) Lec15.67 Lec15.68

18 Scoreboard Example: Cycle Integer Mult1 Add 0 Divide Yes Div F10 F0 F6 61 FU Divide Scoreboard Example: Cycle Integer Mult1 Mult2 Add Divide 62 FU Lec15.69 Lec15.70 Review: Scoreboard Example: Cycle Integer Mult1 Mult2 Add Divide 62 FU,QRUGHULVVXHRXWRIRUGHUH[HFXWH FRPPLW Lec15.71 CDC 6600 Scoreboard Speedup 1.7 from compiler; 2.5 by hand BUT slow memory (no cache) limits benefit Limitations of 6600 scoreboard: forwarding hardware Limited to instructions in basic block (small window) Small number of functional units (structural hazards), especially integer/load store units Do not issue on structural hazards Wait for WAR hazards Prevent WAW hazards Lec15.72

19 Summary #1 Compiler Scheduling HW exploiting ILP Works when can t know dependence at compile time. Code for one machine runs well on another Key idea of Scoreboard: Allow instructions behind stall to proceed (Decode => Issue instr & read operands) Enables out-of-order execution => out-of-order completion ID stage checked both for structural & data dependencies Original version didn t handle forwarding. automatic register renaming Lec15.73