8088/8086 Programming Integer Instructions and Computations

Transcription

1 Unit3 reference 2

2 8088/8086 Programming Integer Instructions and Computations Introduction Up to this point we have studied the software architecture of the 8088 and 8086 microprocessors, their instruction set, addressing modes, and the software development tools provided by the DEBUG program of DOS. We found that the software architectures of the 8088 and 8086 microprocessors are identical and learned how to encode assembly language instructions in machine language and how to use the debugger to enter, execute, and debug programs. In this chapter, we begin a detailed study of the instruction set of the 8088 and 8086 microprocessors. The instructions provide the ability to write simple programs. The following topics are presented in this chapter: Data-Transfer instructions Arithmetic instructions Logic Instructions Shift Instructions Rotate Instructions 5.1 Data Transfer Instructions The 8088 microprocessor has a group of data transfer instructions that are provided to move data either between its internal registers or between an internal register and a storage location in memory. This group includes the move byte or word (MOV) instruction, exchange byte or word (XCHG) instruction, translate byte (XLAT) instruction, load effective address (LEA) instruction, load data segment (LDS) instruction, and load extra segment (LES) instruction. The MOV Instruction The move instruction was briefly introduced in Section 3.4 and used in Section 3.5 to demonstrate the addressing modes of the processor. The move (MOV) instruction shown in Fig. 5 1 (a) is used to transfer a byte or a word of data from a source operand to a destination operand. Earlier we had found that the operands can be internal registers of the 8088 and storage locations in memory. Figure 5-1(b) shows the valid source and destination operand variations. MOV instruction cannot transfer data directly between a source and destination, which both reside in external memory. Instead, the data must first be moved from memory into an internal register, with one MOV instruction and then moved to the new location in memory with a second MOV instruction. All transfers between general-purpose registers and memory can involve either a byte or word of data. The fact that the instruction corresponds to byte or word data is designated by the way in which its operands are specified. For instance, AL or AH would be used to specify a byte operand, and AX, a word operand. On the other hand, data moved between one of the general-purpose registers and a segment register or between a segment register and a memory location must always be word-wide.

3

4 In Fig. 5 1(a), we also find additional important information. For instance, flag bits within the 8088 are not modified by the execution of a MOV instruction. An example of a segment register to general-purpose register MOV instruction shown in Fig. 5 1(c) is MOV DX, CS In this instruction, the code segment register is the source operand, and the data register is the destination. It stands for move the contents of CS into DX. That is, (CS) (DX) For example, if the contents of CS are , execution of the instruction MOV DX, CS as shown in Fig. 5 1(d) makes (DX) = (CS) = In all memory reference MOV instructions, the machine code for the instruction includes an offset address relative to the current contents of the data segment register. An example of this type of instruction is MOV [SUM], AX In this instruction, the memory location identified by the variable SUM is specified using direct addressing. That is, the value of the offset SUM is encoded in the two byte locations that follow its opcode. Let us assume that the content of the DS equals and that SUM equals Then this instruction means move the contents of accumulator AX to the memory location offset by from the starting location of the current data segment. The physical address of this location is obtained as PA = = Thus the effect of the instruction is (AL) (Memory Location ) and (AH) (Memory Location ) Example What is the effect of executing the instruction? MOV CX, [SOURCE_MEM] Where SOURCE_MEM equal to 2016 is a memory location offset relative to the current data segment starting at address 1A Solution Execution of this instruction results in the following: ((DS) ) (CL) ((DS) ) (CH) In other words, CL is loaded with the contents held at memory address 1A =1A Example Use the DEBUG program on the PC to verify the operation of the instruction in Example 5.1. Initialize the word storage location pointed to by SOURCE_MEM to the value AA55 16 before executing the instruction.

5 Solution After invoking the DEBUG program, to determine the memory locations the debugger assigns for use in entering the instructions and data, we can examine the state of the internal registers with the command -R ( ) Looking at the displayed information in Fig 5-2, we find that the contents of CS and IP indicate that the starting address in the current code segment is 1234:0100 and the current data segment starts at address 1234:0000. Initial value of CX is 0000H. To enter instruction from Example 5.1 at location 1234:0100, we use the Assemble command -A ( ) 1234:0100 MOV CX, [20] ( ) 1234:0104 ( ) Now let us redefine the data segment so that it starts at 1A000H. Register command loads the DS register with 1A00H. This entry is -R DS ( ) DS 1234 : 1A00 ( ) Now we initialize the memory locations at addresses 1A00:20 and 1A00:21 to 55H and AAH respectively, with the Enter command -E AA ( ) Finally to execute the instruction, a Trace command is issued -T ( ) Observe that CX has been loaded with AA55H. A use of move instruction is to load the initial address and data values into the registers of the MPU. For instance, in order to initialize the segment registers, the initial values of the segment base addresses are first loaded onto the AX register and then copied onto appropriate segment registers. This is done as immediate data cannot be moved into the segment registers. The XCHG Instruction In our study of the move instruction, we found that it could be used to copy the contents of a register or a memory location into another register or contents of a register into a storage location in memory. In all of these cases, original contents of the source location are preserved and the original contents of the destination location are destroyed. In some applications we need to exchange the contents of two registers. This could be done by using multiple move instructions and storage of the data in a temporary register. However to perform the exchange function more efficiently, a special instruction, the exchange (XCHG) instruction has been provided in the instruction set of Mnemonic Meaning Format Operation Flags affected XCHG Exchange XCHG D, S (D) (S) None (a)

6 Destination Source Accumulator Reg16 Memory Register Register Register Register Memory (b) Figure 5-3 XCHG data transfer instruction (a) Format (b) Valid Operands. Figure shows that the data can be swapped between two general purpose registers or between a general purpose register and a storage location in memory. It allows for the exchange of words of data between one of the general purpose registers, including pointers and index registers and the accumulator, exchange of a byte or word of data between one of the general purpose registers and a storage location in memory, or between two of the general purpose registers. Let us consider a typical example XCHG AX, DX Its execution by the 8088 swaps the contents of AX with that of DX. That is, (AX original) (DX) (DX original) (AX) or (AX) (DX) The XLAT Instruction The translate (XLAT) instruction has been provided in the instruction set of the 8088 to simplify implementation of the lookup-table operation. This instruction is described in the following figure. When using XLAT, the contents of the register BX represent the offset of the starting address of the lookup-table from the beginning of the current data segment. Also, the contents of AL represent the offset of the element to be accessed from the beginning of the lookup-table. This 8- bit element address permits a table with up to 256 elements. The values in both of these registers must be initialized prior to execution of the XLAT instruction. Mnemonic Meaning Format Operation Flags affected XLAT Translate XLAT ((AL)+(BX)+(DS)0 (AL) None Figure 5-4 Format of the XLAT instruction Execution of the XLAT instruction replaces the contents of AL by the contents of the accessed lookup-table location. The physical address of this element in the table is derived as PA = (DS) 0 + (BX) + (AL). The most common application of this instruction is for software code conversions. LEA, LDS, and LES Instructions An important type of data transfer operation is loading a segment and a general purpose register with an address directly from memory.

7 Special instructions are provided in the instruction set of 8088 to give a programmer this capability. These instructions are load register with effective address (LEA), load register and data segment register (LDS) and load register and extra segment register (LES). These instructions provide programmers with the ability to manipulate memory addresses by loading either a 16-bit offset address into a general-purpose register or a 16 bit offset address into a general purpose register together with a 16-bit segment register address into either DS or ES. The LEA instruction is used to load a specified register with a 16-bit offset address. An example of this instruction is LEA SI, EA When executed, it loads the SI register with the offset address value represented by the effective address EA. The value of EA can be specified by any valid addressing mode, say, for instance, if the value in DI equals 1000H and that in BX equals 20H, then executing the instruction LEA SI, [DI + BX +5H] Will load the value EA = 1000H + 20H + 5H= 1025H That is, (SI) = 1025H The other two instructions, LDS and LES are similar to LEA except that they load the specified register as well as the DS or ES segment register respectively. That is they are able to load a complete address pointer that is stored in memory. In this way, executing a single instruction can activate a new data segment. Earlier we showed how the segment registers, index registers and data registers of the MPU can be initialized with immediate data. Another way of initializing them is from a table of data in memory. Using the LES instruction along with the MOV instruction provides an efficient method for performing register initialization from a data table. 5.2 Arithmetic Instructions The instruction set of the 8088 microprocessor contains a variety of arithmetic instructions. They include instructions for the addition, subtraction, multiplication and division operations. These operations can be performed on numbers expressed in a variety of numeric data formats. The status that results from the execution of an arithmetic instruction is recorded in the flags of the microprocessor. The flags that are affected by the arithmetic instructions are carry flag (CF), auxiliary flag (AF), sign flag (SF), zero flag (ZF), parity flag (PF), and overflow flag (OF). The following table summarizes the various arithmetic instructions.

8 ADD ADC INC AAA DAA SUB SBB DEC NEG AAS DAS MUL IMUL AAM DIV IDIV AAD CBW CWD Addition Add byte or word Add byte or word with carry Increment byte or word by 1 ASCII adjust for addition Decimal adjust for addition Subtraction Subtract byte or word Subtract byte or word with borrow Decrement byte or word by 1 Negate byte or word ASCII adjust for subtraction Decimal adjust for subtraction Multiplication Multiply byte or word unsigned Integer multiply byte or word ASCII adjust for multiplication Division Divide byte or word unsigned Integer divide byte or word ASCII adjust for division Convert byte to word Convert word to double word Figure 5-5 Arithmetic Instructions Addition Instructions: ADD, ADC, INC, AAA and DAA The following figure 5-6(a) shows the form of each of the instructions in the addition subgroup; Figure 5-6(b) shows allowed operand variations for all but the INC instruction; and Figure 5-6(c) shows the allowed operands for the INC instruction. The ADD instruction can be used to add an immediate operand to the contents of the accumulator, the contents of another register or the contents of a storage location in memory. It allows us to add the contents of two registers or the contents of a register and a storage location in memory. In general the result of executing ADD is expressed as (S) + (D) (D) That is, the contents of the source operand are added to the destination operand and the sum that results is put into the location of the destination operand. The carry-out (C0) that may occur from the addition of the most significant bit of the destination is reflected in the carry flag (CF). Therefore, this instruction performs the half-add binary arithmetic operation.

9 Mnemonic Meaning Format Operation Flags affected ADD Addition ADD D,S (S)+(D) (D) OF,SF,ZF,AF,PF,CF Carry (CF) ADC Add with carry ADC D,S (S)+(D)+(CF) (D) OF,SF,ZF,AF,PF,CF Carry (CF) INC Increment by 1 INC D (D)+1 (D) OF,SF,ZF,AF,PF AAA ASCII adjust for Addition AAA AF,CF OF,SF,ZF,PF DAA Decimal adjust for addition DAA (a) undefined SF,ZF,AF,PF,CF, OF undefined Destination Source Register Register Register Memory Destination Memory Register Reg16 Register Immediate Reg8 Memory Immediate Memory Accumulator Immediate (c) (b) Figure 5-6 Addition Instructions (a) Format (b) Allowed operands for ADD and ADC instructions (c) Allowed operands for INC instructions. Example Assume that the AX and BX registers contain 1100H and 0ABCH respectively. What is the result of executing the instruction ADD AX, BX? Solution Executing the ADD instruction causes the contents of source operand BX to be added to the contents of the destination operand AX. This gives (BX) + (AX) = 0ABC = 1BBC 16 This sum ends up in the destination register AX. That is, (AX) = 1BBC 16 The carry-out does not occur; therefore the carry flag is reset. CF= 0 Execution of this instruction is illustrated in Figs. 5-7(a) and (b).

10 Example Use the DEBUG program to verify the execution of the instruction in Example 5.7. Assume that the registers are to be initialized with the values shown in Fig. 5-7(a). Solution: The DEBUG sequence for this is shown in Fig 5-8.

11 After the DEBUG program is brought up, the instruction is assembled into memory with the command -A 1100:0100 (ENTER) 1100:0100 ADD AX, BX (ENTER) 1100:0102 (ENTER) Next, as shown in Fig. 5-13, the AX and BX registers are loaded with the values and 0ABC 16 respectively, using R commands -R AX AX 0000:1100 -R BX BX 0000:0ABC Next, the loading of the instructions is verified with the Unassemble command -U 1100: and is shown in fig.5-8 to be correct. We are now ready to execute the instructions with the Trace command -T = 1100:0100

12 From the trace dump in fig. 5-8, we see that the sum of AX and BX, which equals 1BBCH, is now held in destination register AX. Also note that no carry (NC) has occurred. The instruction add with carry (ADC) works similarly to ADD. But in this case, the content of carry flag is also added that is, (S) + (D) + (CF) (D) Here CF serves as both C i and C 0, and the instruction performed the operation of the full adder logic function. The valid operand combinations are the same as those for the ADD instruction. ADC is primarily used for multiword add operations. Another instruction that can be considered part of the addition subgroup of arithmetic instructions is the increment (INC) instruction. As shown in the Fig. 5-6(c) its operands can be the contents of 16 bit register, an 8-bit internal register, or a storage location in memory. Execution of INC instruction adds 1 to the specified operand. An example of an instruction that increments the high byte of AX is INC AH This instruction is typically used to increment the values of a count or address. Fig 5-6(a) shows how the execution of these three instructions affects the earlier mentioned flags. Example The original contents of AX, BL, word-sized memory location SUM, and carry flag CF are 1234H, ABH, 00CDH, and 0H, respectively. Describe the results of executing the following sequence of instructions: ADD AX, [SUM] ADC BL, 05H INC WORD PTR [SUM] Solution Executing the first instruction adds the word in the accumulator and the word in the memory location pointed to by address SUM. The result is placed in the accumulator. That is, (AX) (AX) + (SUM) = 1234H + 00CDH = 1301H The carry flag remains reset. The second instruction adds to the lower byte of the base register (BL) the immediate operand 5H and the carry flag, which is 0H. This gives (BL) (BL) + imm8 + (CF) = ABH + 5H+ 0H = B0H Since no carry is generated CF remains reset. The last instruction increments the contents of memory location SUM by one. That is, (SUM) (SUM) + 1H = 00CDH + 1H =00CEH

13 Example Verify the operation of the instruction sequence in Ex5.9 by executing it with the DEBUG. A source program that includes this sequence of instructions is shown in Fig.5-17 (a), whose source listing is shown in the Fig 5-17(b), which can be referred to from the textbook. A run module that was produced by linking this program is stored in file EX510.EXE Solution The DEBUG program is brought up and at the same time the run module from the file EX510.EXE is loaded with the command C:\ DOS > DEBUG A: EX510.EXE ( ) Next, we will verify the loading of the program by unassembling it with the command -U 0 12 Comparing the displayed instruction sequence in Fig. 5-`7 to the source listing in Fig.5-17(b), we find that the program has loaded correctly. Notice that in Fig. 5-17(c) that the instructions for which we are interested in verifying operation start at the address 0D03: 000A. For this reason, a Go command will be used to execute down to this point in the program. This command is -G A ( ) Note that the trace information displayed for this command, CS now contains 0D03H and IP contains 000AH; therefore, the next instruction to be executed is at the address 0D03: 000A. This is the ADD instruction. Now we need to initialize the registers AX, BX and the memory location pointed to by SUM (WORD PTR [0000]). We must also ensure that the status of the carry flag is set to NC (No carry). Now we are ready to execute the ADD instruction. This is done by issuing the command -T ( ) From the information displayed for this command in Fig. 5-17(c), note that the value CD16 has been added to the original value in AX, which was , and the sum that results in AX is Next the ADC instruction is executed with another T command. -T ( ) This causes the immediate operand value to be added to the original contents of BL, AB 16, and the sum that is produced in BL is B0 16. The last instruction is executed with one more T command, causing the SUM (WORD PTR [0000]) to be incremented by 1. This can be verified by issuing the DUMP command -D 0 1(enter)

14 Note that the value of SUM is identified as a WORD PTR. This assembler directive means that the memory location for SUM is to be treated as a word-wide storage location. Similarly if a byte- wide storage location, say BYTE_LOC, is to be accessed, it would be identified as BYTE PTR [BYTE_LOC]. The addition instructions we just covered can be also used to add numbers expressed in ASCII code provided the binary result that is produced is converted back to its equivalent ASCII representation. This eliminates the need for doing a code conversion on ASCII data prior to processing it with addition operations. Whenever the 8088 does an addition on ASCII format data, an adjustment must be performed on the binary result to convert it to the equivalent decimal number. It is specifically for this purpose that the ASCII adjusts for addition (AAA) instruction is provided in the instruction. The AAA instruction should be executed immediately after the ADD instruction that adds ASCII data. Assuming that AL contains the result produced by adding two ASCII coded numbers, execution of the AAA instruction causes of AL to be replaced by its equivalent decimal value. If the sum is greater than nine, AL contains the LSD and AH is incremented by 1. Otherwise, AL contains the sum and AH is unchanged. Figure 5-6(a) shows that the AF and CF flags can be affected. Since AAA can adjust only the data that are in AL, the destination register for ADD instructions that process ASCII numbers should be AL. Example What is the result of executing the following instruction sequence? ADD AL, BL AAA Assume that AL contains (the ASCII code for number 2) and BL contains (ASCII code for number 4), and that AH has been cleared. SOLUTION: Executing the ADD instruction gives (AL) (AL) + (BL) = = Next, the result is adjusted to give its equivalent decimal number. This is done by execution of the AAA instruction. The equivalent of adding 2 and 4 is decimal 6 with no carry). Therefore, the result after the AAA instruction is and both AF and CF remain cleared. (AL) = (AH) = 00 16

15 The instruction set of the 8088 includes another instruction, called decimal adjust for addition (DAA). This instruction is used to perform an adjust operation similar to the performed by AAA but for the addition of packed BCD numbers instead of ASCII numbers. Information about this instruction is also provided in Fig Similar to AAA, DAA performs an adjustment on the value in AL. A typical instruction sequence is ADD AL, BL DAA Remember that the contents of AL and BL must be packed BCD numbers, that is, two BCD digits packed into a byte. The adjusted result in AL is again a packed BCD byte. As an example of the use of the instructions covered in this section, let us perform a 32-bit binary add operation on the contents of the processor s registers. We will implement the addition (DX, CX) (DX, CX) + (BX, AX) For the following data in the registers: (DX, CX) = FEDCBA98 16 (BX, AX) = We first initialize the registers with the data using move instructions as follows: MOV DX, 0FEDCH MOV CX, OBA98H MOV BX, 0123H MOV AX, 4567H Next, the 16 least significant bits of the 32-bit number are added with the instructions: ADD CX, AX Note that the result from this part of the addition is in CX and the carry flag. To add the most significant 16 bits, we must account for the possibility of a carry out from the addition of the lower 16 bits. For this reason, the ADC instruction must be used. Thus the last instruction is ADC DX, BX. Execution of this instruction produces the upper 16 bits of the 32-bit sum in register DX.

16 SUBTRACTION INSTRUCTIONS: SUB, SBB, DEC, AAS, DAS, and NEG The instruction set of the 8088 includes an extensive set of instructions provided for implementing subtraction. Mnem Meaning Format Operation Flags affected onic SUB Subtract SUB D,S (D) - (S) (D) OF, SF, ZF, AF, PF, CF Borrow CF) SBB Subtract with borrow SBB D,S (D)-(S)-(CF) (D) OF, SF, ZF, AF, PF, CF DEC Decrement by 1 DEC D (D)-1 (D) OF, SF, ZF, AF, PF NEG Negate NEG D 0 - (D) (D) OF, SF, ZF, AF, PF, CF 1 (CF) DAS Decimal adjust for DAS SF, ZF, AF, PF, CF subtraction OF undefined AAS ASCII adjust AAS AF, CF for subtraction OF, SF, ZF, PF undefined (a) Destination Source Register Register Register Memory Memory Register Accumulator Immediate Register Immediate Memory Immediate (b) Destination Reg 16 Reg 8 Memory (c) Destination Register Memory (d) Figure 5-19 (a) Subtraction instructions. (b) Allowed operands for SUB and SBB instructions. (c) Allowed operands for DEC instruction. (d) Allowed operands for NEG instruction. As shown in Fig 5-19(a), the subtraction subgroup is similar to the addition subgroup. It includes instructions for subtracting a source and a destination operand, decrementing an operand, and adjusting the result of subtractions of ASCII and BCD data. An additional instruction in this subgroup is negate. The subtract (SUB) instruction is used to subtract the value of a source operand from a destination operand. The result of this operation in general is given as

17 (D) (D) (S) As shown in Fig. 5-19(b), it can employ operand combinations similar to the ADD instruction. The subtract with borrow (SBB) instruction is similar to SUB; however, it also subtracts the contents of the carry flag from the destination. That is, (D) (D) (S) (CF) CF serves as both Br i and Br 0 and the instruction performs the operation of the fullsubtractor logic function. SBB is primarily used for multiword subtract operations. Example Assuming that the contents of the registers BX and CX are and , respectively, and the carry flag is 0, what is the result of executing the following instruction? SBB BX, CX Solution Since the instruction implements the operation (BX) (CX) (CF) (BX) We get (BX) = 1234H 0123H -0H = 1111H Since no borrow was needed carry flag remains cleared. Just as the INC instruction can be used to add 1 to an operand, the decrement (DEC) instruction can be used to subtract 1 from its operand. The allowed operands for DEC are shown in Fig.5-19(c). In Fig.5-19(d) we see that the negate instruction (NEG) can operate on operands in a general-purpose register or a storage location in memory. Executing this instruction causes the value of its operand to be replaced by its negative. This is actually done through subtraction- that is, the contents of the specified operand are subtracted from zero and the result is returned to the operand location. The subtraction is actually performed by the processor hardware using 2 s complement arithmetic. To obtain the correct value of the carry flag that results from a NEG operation, the carry generated by the add operation used in the 2 s complement subtraction calculation must be complemented. Example Assuming that register BX contains 003AH, what is the result of executing the following instruction? NEG BX Solution Executing NEG instruction causes the 2 s complement subtraction that follows: (BX) = 0000H (BX) = s complement of 003AH

18 = 0000H + FFC6H = FFC6H Since no carry is generated in this add operation, the carry flag is complemented to give (CF)= 1 Example Verify the operation of the NEG instruction in Example 5.14 by repeating the example using DEBUG program. Solution After starting the DEBUG program, we first initialize the contents of the BX register. This is done with the command - R BX ( ) BX 0000 : 3A ( ) - Next the instruction is assembled with the command -A ( ) 1234:0100 NEG BX ( ) 1234:0102 ( ) At this point we can verify the initialization of BX by issuing the command -R BX ( ) BX 003A : ( ) - To check the assembly of the instruction, unassembled it with the command -U ( ) 1234:0100 F7DB NEG BX - Now the instruction is executed with the command -T ( ) Observe from the results the new contents of BX as FFC6H, which is the negative of 003AH. Also observe that the carry flag is set. In our study of addition instruction subgroup, we found that the 8088 is capable of directly adding ASCII and BCD numbers. The SUB and SBB instructions can subtract numbers represented in these formats as well. Just as for addition, the results that are obtained must be adjusted to produce the corresponding decimal numbers. In the case of ASCII subtraction, we use the ASCII adjust for subtraction (AAS) instruction, and for packed BCD subtraction we use the decimal adjust for subtract (DAS) instruction. An example of an instruction sequence for direct ASCII subtraction is SUB AL, BL AAS

19 ASCII numbers must be loaded into AL and BL before the subtract instruction is executed. Note that the destination of the subtraction should be AL. After execution of AAS, AL contains the difference of the two numbers, and AH is unchanged if no borrow takes place or is decremented by 1 if a borrow occurs. As an example of the use of the subtraction instructions, let us implement a 32-bit subtraction of two numbers X and Y that are stored in memory as X = (DS: 203H) (DS: 202H) (DS: 201H) (DS: 200H) MS byte of LS byte of MS byte of LS byte of MS word MS word LS word LS word Y = (DS: 103H) (DS: 102H) (DS: 101H) (DS: 100H) The result of X Y is to be saved in the place where X is stored in memory. First, we subtract the least significant 16 bits of the 32-bit words using the instructions MOV AX, [200H] SUB AX, [100H] MOV [200H], AX Next, the most significant words of X and Y are subtracted. In this part of the 32-bit subtraction, we must use the borrow that might have been generated by the subtraction of the least significant words. Therefore, SBB is used to perform the subtraction operation. The instructions to do this are MOV AX, [202H] SBB AX, [102H] MOV [202H], AX These instructions used direct addressing mode to access data in memory. The 32-bit subtract operation can also be done with indirect addressing with the program shown in Figure 5-22 below. MOV SI, 200H; Initialize pointer for X MOV DI, 100H; Initialize pointer for Y MOV AX, [SI] SUB AX, [DI]; Subtract LS words MOV [SI], AX; Save the LS word of result MOV AX, [SI] +2; SBB AX, [DI] +2; Subtract MS words MOV [SI] +2, AX; Save the MS word of result Figure bit subtraction program using indirect addressing. Multiplication and Division Instructions: MUL, DIV, IMUL, IDIV, AAM, AAD, CBW, and CWD The 8088 has instructions to support multiplication and division of binary and BCD numbers. Two basic types of multiplication and division instructions, for the processing of unsigned numbers and signed numbers, are available. To do these operations on unsigned numbers, the instructions are MUL and DIV. On the other hand, to multiply or divide 2 s complement signed numbers, the instructions are IMUL and IDIV. Figure 5-23(a) describes these instructions. Note that in Figure 5-23(b) a single bytewide or word-wide operand is specified in a multiplication instruction. It is the source

20 operand. As shown in Figure 5-23(a), the other operand, which is the destination, is assumed already to be in AL for 8-bit multiplication or in AX for 16-bit multiplication. Mnemonic Meaning Format Operation Flags affected MUL Multiply (unsigned) MUL S OF, CF SF,ZF,AF,PF undefined DIV Division DIV S OF, SF, ZF, AF, PF, CF (unsigned) undefined. IMUL IDIV AAM AAD CBW CWD Integer multiply (signed) Integer divide (signed) Adjust AL for multiplication Adjust AX for division Convert byte to word Convert word to double word IMUL S IDIV S AAM AAD CBW CWD (AL).(S8) (AX) (AX).(S16) (DX).(AX) (i) Q((AX)/(S8)) (AL) R((AX)/(S8)) (AH) (ii) Q((DX,AX)/(S16)) (AX) R((DX,AX)/(S16)) (DX) If Q is FFH in case (i) or FFFFH in case (ii) then type 0 interrupt occurs. (AL).(S8) (AX) (AX).(S16) (DX).(AX) (i) Q((AX)/(S8)) (AL) R((AX)/(S8)) (AH) (ii) Q((DX,AX)/(S16)) (AX) R((DX,AX)/(S16)) (DX) If Q is positive and exceeds 7FFFH or if Q is negative and becomes less than 8001H, then type 0 interrupt occurs. (AH).10 + (AL) (AL) 00 (AH) Q ((AL/10)) (AH) R((AL/10)) (AL) (MSB of AL) (All bits of AH) (MSB of AX) (All bits of DX) (a) Source OF, CF SF,ZF,AF,PF undefined OF, SF, ZF, AF, PF, CF undefined. SF, ZF, PF OF, AF, CF undefined SF, ZF, PF OF, AF, CF undefined None Reg8 Reg16 Mem8 Mem16 (b) Figure 5-23 Multiplication and Division arithmetic instructions (a) Format (b) Valid operands. The result of executing an MUL or IMUL instruction on byte data can be represented as (AX) (AL) * (8-bit operand) That is, the resulting 16-bit product is produced in the AX register. On the other hand, for multiplication of data words, the 32-bit result is given by (DX, AX) (AX) * (16-bit operand), where AX contains the 16 LSBs and DX the 16 MSBs. None

21 For the division operation, again just the source operand is specified. The other operand is either the contents of AX for 16-bit dividends or the contents of both DX and AX for 32-bit dividends. The result of a DIV or IDIV instruction for an 8-bit divisor is represented by (AH), (AL) (AX)/ (8-bit operand) where AH contains the remainder and AL the quotient. For 16-bit division, we get (DX), (AX) (DX, AX)/ (16-bit operand) Here AX contains the quotient and DX contains the remainder. Example The 2 s complement signed data contents of AL equal -1 and the contents of CL are -2. What result is produced in AX by executing the following instructions? MUL CL And IMUL CL Solution As binary data, the contents of AL and CL are (AL) = -1 (as 2 s complement) = = FFH (CL) = -2 (as 2 s complement) = = FEH Executing the MUL instruction gives (AX) = * = = FD02H The second instruction multiplies the two numbers as signed numbers to generate the signed result. That is, (AX) = -1H * -2H = 2H = 0002H Example Verify the operation of the MUL instruction in Example 5.16 by performing the same operation with the DEBUG program. Solution First, the DEBUG program is loaded, and then registers AX and CX are initialized with the values FFH and FEH respectively. These registers are loaded as follows: - R AX ( ) AX 0000 : FF ( ) - R CX ( ) CX 0000 : FE ( ) - Next, the instruction is loaded with the command - A ( ) 1234:0100 MUL CL 1234:0102 ( ) - Before executing the instruction, let us verify the loading of AX, CX and the instruction. To do this, we use the commands as follows:

22 -R AX ( ) AX 00FF : ( ) -R CX ( ) CX 00FE : ( ) -U ( ) 1234:0100 F6E1 MUL CL - To execute this command, we issue the T command as follows: -T ( ) The displayed result in Fig shows that AX now contains FD02H, the unsigned product of FFH and FEH. As Figure 5-23(a) shows, adjust instructions for BCD multiplication and division are also provided. They are adjust AX for multiply (AAM) and adjust AX for divide (AAD). The AAM instruction assumes that the instruction just before it multiplies two unpacked BCD numbers with their product produced in AL. The AAD instruction assumes that AH and AL contains unpacked BCD numbers. The division instructions can also be used to divide an 8-bit dividend in AL by an 8- bit divisor. However, to do this, the sign of the dividend must first be extended to fill the AX register. That is, AH is filled with zeros if the number in AL is positive or with ones if it is negative. Execution of the convert byte to word instruction (CBW) automatically does this conversion. Note that the sign extension does not change the signed value for the data. It simply allows data to be represented using more bits. In a similar way, the 32-bit by 16-bit division instructions can be used to divide a 16-bit dividend in AX by a 16-bit divisor. In this case, the sign bit of AX must be extended by 16 bits into the DX register. This can be done by another instruction, known as convert word to double word (CWD). Figure 5-23(a) shows the operations of these two sign extension instructions. Note that the CBW and CWD instructions are provided to handle operations where the result or intermediate results of an operation cannot be held in the correct word length for use in other arithmetic operations. Using these instructions, we can extend the value of a byte- or word-wide signed number to its equivalent signed word or double- word value. 5.3 Logic Instructions The 8088 has instructions for performing the logic operations AND, OR, exclusive-or, and NOT. The instructions that this processor provides performs these basic logic operations bit-wise on byte- and word-wide data. As shown in Figure 5-27(a), the AND, OR, and XOR instructions perform their respective logic operations bit by bit on the specified source and destination operands, the result being represented by the final contents of the destination operand. Figure 5-27(b) shows the allowed operand combinations for the AND, OR, and XOR instructions.

23 For example, the instruction AND AX, BX This causes the contents of BX to be bit-wise ANDed with the contents of AX. The result is reflected by the new contents of AX. Assuming that AX contains 1234H and BX contains 000FH, the result produced by the instruction is 1234H.000FH = = = 0004H The result is stored in the destination operand and gives (AX) = 0004H Note that the 12 most significant bits are zeros. In this way, we see how the AND instruction is used to mask the 12 MSBs of the destination operand. Mnemonic Meaning Format Operation Flags affected AND OR XOR NOT Logical AND Logical Inclusive- OR Logical Exclusive- OR Logical NOT AND D, S OR D, S XOR D, S NOT D (S).(D) (D) (S)+(D) (D) (S) (D) (D) not (D) (D) OF,SF,ZF, PF, CF AF undefined OF,SF,ZF, PF, CF AF undefined OF,SF,ZF, PF, CF AF undefined None (a) Destination Source Register Register Register Memory Memory Register Register Immediate Memory Immediate Destination Accumulator Immediate Register Memory (b) (c) Figure 5-27 Logic Instructions (a) Format (b) Valid Operands for AND, OR and XOR instructions (c) Valid Operands for NOT instruction. The NOT logic instruction differs from those for AND, OR, and exclusive-or in that it operates on a single operand. Figure 5-27(c) shows the allowed operands for the NOT instruction. High-level languages, such as C, allow programmers to write statements that perform these bit-wise logic operations on variables. The C compiler implements the operation for these statements by applying the logic instructions of the processor s instructions set. Clearing, Setting, and Toggling Bits of an Operand A common use of logic instructions is to mask a group of bits of a byte/word of data. By mask, we mean to clear the bit or bits to zero.

24 Remember that when a bit is ANDed with another bit that is at logic 0, the result is always 0. On the other hand, if a bit is ANDed with a bit that is at logic 1, its value remains unchanged. Thus we see that the bits that are to be masked must be set to 0 in the mask, which is the source operand, and those that are to remain unchanged are set to 1. For instance, consider the following instruction AND AX, 000FH The mask equals 000FH; therefore it would mask off the upper 12 bits of the word of data in destination AX. Let us assume that the original value in AX is FFFFH. Then executing the instruction performs the operation = (AX) = 000FH. This shows that just the lower 4 bits in AX remain intact. The OR instruction ca be used to set a bit or bits in a register or a storage location in memory to logic 1.If a bit is ORed with another bit that is 0, the value of the bit remains unchanged; however, if it is ORed with another bit that is 1, the bit becomes 1. For instance, let us assume that we want to set bit B 4 of the byte at the offset address CONTROL_FLAGS in the current data segment of memory to logic 1. This can be done with the following instruction sequence: MOV AL, [CONTROL_FLAGS] OR AL, 10H MOV [CONTROL_FLAGS], AL First the values of the flags are copied into AL and the following logic operation is performed. (AL) = XXXXXXXX = XXX1XXXX 2 Finally, the new byte in AL, which has bit B 4 set to 1, is written back to the memory location called CONTROL_FLAGS. The XOR instruction can be used to reverse the logic level of a bit or bits in a register or storage location in memory. This operation is referred to as toggling the bit. 5.4 Shift Instructions The four shift instructions of the 8088 can perform two basic types of shift operations; the logical shift and the arithmetic shift. Moreover, each of these operations can be performed to the right or to the left. The shift instructions are shift logical left (SHL), shift arithmetic left (SAL), shift logical right (SHR), and shift arithmetic right (SAR). These instructions are used to align data, isolate bits of a byte or a word so that it can be tested, and to perform simple multiply and divide computations. SHL, SHR, SAL, and SAR Instructions The operation of the logical shift instructions, SHL and SHR, is described in Fig. 5-30(a). Note that in Fig 5-30(b) that the destination operand, the data whose bits are to be shifted, can be either the contents of an internal register or a storage location in memory.

25 Mnemonic Meaning Format Operation Flags affected SAL/SHL Shift arithmetic SAL D, count SHL D, count CF, PF, SF, ZF AF undefined left/shift OF undefined if logical left count 1 SHR Shift SHR D, count CF, PF, SF, ZF logical AF undefined right OF undefined if count 1 SAR Destination Register Register Memory Memory Shift arithmetic right (b) Count 1 CL 1 CL SAR D, count Shift the (D) left by the number of bit positions equal to the count and fill the vacated bits positions on the right with zeros. Shift the (D) right by the number of bit positions equal to the count and fill the vacated bits positions on the left with zeros. Shift the (D) right by the number of bit positions equal to the count and fill the vacated bits positions on the left with the original MSB. (a) CF, PF, SF, ZF AF undefined OF undefined if count 1 Figure 5-30 Shift Instructions (a) Format (b) Valid Operands. Moreover, the source operand can be specified in two ways. If it is assigned the value 1, a 1-bit shift will take place. For instance, as illustrated in Fig 5-31(a) from text book, executing SHR AX, 1 Causes the 16-bit contents of the AX register to be shifted 1 bit position to the left. Here we see that the vacated LSB location is filled with zero and the bit shifted out of the MSB is saved in CF. On the other hand, if the source operand is specified as CL instead of 1, the count in this register represents the number of bit positions the contents of the operand are to be shifted. This permits the count to be defined under software control and allows a range of shifts from 1 to 255 bits. An example of an instruction specified in this way is SHR AX, CL Assuming that CL contains the value 02H, the logical shift right that occurs is as shown in the fig 5-31(b). Note that the two MSBs have been filled with zeros and the last bit shifted out at the LSB, which is zero, is placed in the carry flag. In an arithmetic shift to the left, the SAL operation, the vacated bits at the right of the operand are filled with zeros, whereas in an arithmetic shift to the right, the SAR operation, the vacated bits at the left are filled with the value of the original MSB of the operand. Thus, in an arithmetic shift to the right, the original sign of the number is maintained. This operation is equivalent to division by powers of 2 as long as the bits shifted out of the LSB are zeros.

26 Isolating the Value of a Bit in an Operand A frequent need in programming is to isolate the value of one of the bits of a word or byte of data by shifting it into the carry flag. The shift instructions may perform this operation on data wither in a register or a storage location in memory. The instructions that follow perform this type of operation on a byte of data stored in memory at address CONTROL_FLAGS: MOV AL, [CONTROL_FLAGS] MOV CL, 04H SHR AL, CL The first instruction reads the value of the byte of data at address CONTROL_FLAGS into AL. Next, a shift count for four is loaded into CL, and then the value in AL is shifted to the right four bit positions. Since the MSBs of AL are reloaded with zeros as part of the shift operation, the results are (AL) = 0000B 7 B 6 B 5 B 4 and (CF) = B 3 In this way, we see that the bit B 3 of CONTROL_FLAGS has been isolated by placing it in CF. Once this bit is in CF, it can be tested by other instructions and based on this value initiate another software operation. 5.5 Rotate Instructions Another group of instructions, the rotate instructions, are similar to the shift instructions we just introduced. This group includes the rotate left (ROL), rotate right (ROR), rotate left through carry (RCL), and rotate right through carry (RCR) instructions. They perform many of the same programming functions as the shift instructions, such as alignment of data and isolation of a bit of an element of data. ROL, ROR, RCL, and RCR Instructions These instructions have the capability to rotate the contents of either an internal register or a storage location in memory. Also, the rotation that takes place can be from 1 to 255 bit positions to the left or to the right. Moreover, in the case of multi bit rotate, the number of bit positions to be rotated is specified by the value in CL. Their difference from the shift instructions lies in the fact that the bits moved out at either the MSB or LSB end are not lost; instead they are reloaded at the other end. As an example, let us look at the ROL instruction. ROL causes the contents of the selected operand to be rotated left the specified number of bit positions. Each bit shifted out at the MSB end is reloaded at the LSB end. Moreover, the content of CF reflects the state of the last bit that was shifted out. The ROR instruction operates the same way as the ROL instruction except that it causes data to be rotated to the right instead of to the left. The other two instructions RCL and RCR differ from ROL and ROR in that the bits are rotated through the carry flag.

27 Alignment of Data in Operands An example of a software operation that can be performed with the rotate instructions is the disassembly of the two hexadecimal digits in a byte of data in memory so that they can be added. For instance, consider the following MOV AL, [HEX_DIGITS] MOV BL, AL MOV CL, 04H ROR BL, CL AND AL, 0FH AND BL, 0FH ADD AL, BL First the byte containing the two hex digits is read into AL. Then, a copy is made in BL. Next, the four most significant bits in BL are moved to the four least significant bits with a rotate operation. This repositions the most significant hex digit of the original byte into the least significant digit position in BL. Now, the most significant hex digits in both AL and BL are masked off. This isolates both the hex digits. Finally, the two hex digits are added together in AL.