#pragma config Usage. #pragma config Settings. #pragma config <setting>=<named value>

Transcription

1 1 z :21 #pragma config Usage #pragma config <setting>=<named value> // Oscillator Selection bits: 11XX External RC oscillator, CLKO function on RA6 // Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor enabled // Internal External Oscillator Switchover bit: Internal External Switchover mode enabled #pragma config OSC = RC, FCMEN = ON, IESO = ON #pragma config <setting>=<literal constant> // Oscillator Selection bits: 11XX External RC oscillator, CLKO function on RA6 // Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor enabled // Internal External Oscillator Switchover bit: Internal External Switchover mode enabled #pragma config OSC = 0xC, FCMEN = 0x1, IESO = 0x1 #pragma config <register>=<literal constant> // Oscillator Selection bits: 11XX External RC oscillator, CLKO function on RA6 // Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor enabled // Internal External Oscillator Switchover bit: Internal External Switchover mode enabled #pragma config CONFIG1H = 0xCC // 0x #pragma config IDLOC0 = 0xFF #pragma config Settings Register: 0x OSC = Oscillator Selection bits RC 11XX External RC oscillator, CLKO function on RA6 RC1 101X External RC oscillator, CLKO function on RA6 IRCIO Internal oscillator block, port function on RA6 and port function on RA7 IRC Internal oscillator block, CLKO function on RA6 and port function on RA7 RC2 External RC oscillator, CLKO function on RA6 HS HS oscillator LP LP oscillator HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ECIO EC oscillator, port function on RA6 EC EC oscillator, CLKO function on RA6 XT XT oscillator

2 2 z :21 RCIO External RC oscillator, port function on RA6 FCMEN = Fail-Safe Clock Monitor Enable bit ON Fail-Safe Clock Monitor enabled OFF Fail-Safe Clock Monitor disabled IESO = Internal External Oscillator Switchover bit ON Internal External Switchover mode enabled OFF Internal External Switchover mode disabled Register: 0x BOREN = Brown-out Reset Enable bits ON Brown-out Reset enabled OFF Brown-out Reset disabled BORV = Brown Out Reset Voltage bits 42 VBOR set to 4.2V 27 VBOR set to 2.7V 45 VBOR set to 4.5V PWRTEN = Power-up Timer Enable bit OFF PWRT disabled ON PWRT enabled Register: 0x WINEN = Watchdog Timer Window Enable bit OFF WDT window disabled ON WDT window enabledbled WDPS = Watchdog Timer Postscale Select bits : : : : : : : : : :16 8 1:8 1 1: : : :2

3 3 z : :64 WDTEN = Watchdog Timer Enable bit ON WDT enabled OFF WDT disabled (control is placed on the SWDTEN bit) Register: 0x T1OSCMX = Timer1 Oscillator MUX ON Low-power Timer1 operation when microcontroller is in Sleep mode OFF Standard (legacy) Timer1 oscillator operation PWMPIN = PWM output pins Reset state control OFF PWM outputs disabled upon Reset (default) ON PWM outputs drive active states upon Reset HPOL = High-Side Transistors Polarity HIGH PWM1, 3, 5 and 7 are active-high LOW PWM1, 3, 5 and 7 are active-low LPOL = Low-Side Transistors Polarity HIGH PWM0, 2, 4 and 6 are active-high LOW PWM0, 2, 4 and 6 are active-low Register: 0x PWM4MX = PWM4 MUX bit RD5 PWM4 output is multiplexed with RD5 RB5 PWM4 output is multiplexed with RB5 MCLRE = MCLR Pin Enable bit ON Enabled OFF Disabled SSPMX = SSP I/O MUX bit RD1 SCK/SCL clocks and SDA/SDI data are multiplexed with RD3 and RD2, respectively. SDO output is multiplexed with RD1. RC7 SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4, respectively. SDO output is multiplexed with RC7. FLTAMX = FLTA MUX bit RC1 FLTA input is multiplexed with RC1 RD4 FLTA input is multiplexed with RD4 EXCLKMX = TMR0/T5CKI External clock MUX bit RC3 TMR0/T5CKI external clock input is multiplexed with RC3 RD0 TMR0/T5CKI external clock input is multiplexed with RD0 Register: 0x300006

4 4 z :21 STVREN = Stack Full/Underflow Reset Enable bit ON Stack full/underflow will cause Reset OFF Stack full/underflow will not cause Reset DEBUG = Background Debugger Enable bit OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug LVP = Low-Voltage ICSP Enable bit ON Low-voltage ICSP enabled OFF Low-voltage ICSP disabled Register: 0x CP0 = Code Protection bit OFF Block 0 ( FFFh) not code-protected ON Block 0 ( FFFh) code-protected CP1 = Code Protection bit OFF Block 1 ( FFF) not code-protected ON Block 1 ( FFF) code-protected CP2 = Code Protection bit OFF Block 2 ( FFFh) not code-protected ON Block 2 ( FFFh) code-protected CP3 = Code Protection bit OFF Block 3 ( FFFh) not code-protected ON Block 3 ( FFFh) code-protected Register: 0x CPB = Boot Block Code Protection bit OFF Boot Block ( FFh) not code-protected ON Boot Block ( FFh) code-protected CPD = Data EEPROM Code Protection bit OFF Data EEPROM not code-protected ON Data EEPROM code-protected Register: 0x30000A WRT0 = Write Protection bit OFF Block 0 ( FFFh) not write-protected ON Block 0 ( FFFh) write-protected WRT1 = Write Protection bit OFF Block 1 ( FFF) not write-protected ON Block 1 ( FFF) write-protected

5 5 z :21 WRT2 = Write Protection bit OFF Block 2 ( FFFh) not write-protected ON Block 2 ( FFFh) write-protected WRT3 = Write Protection bit OFF Block 3 ( FFFh) not write-protected ON Block 3 ( FFFh) write-protected Register: 0x30000B WRTB = Boot Block Write Protection bit OFF Boot Block ( FFh) not write-protected ON Boot Block ( FFh) write-protected WRTC = Configuration Register Write Protection bit OFF Configuration registers ( FFh) not write-protected ON Configuration registers ( FFh) write-protected WRTD = Data EEPROM Write Protection bit OFF Data EEPROM not write-protected ON Data EEPROM write-protected Register: 0x30000C EBTR0 = Table Read Protection bit OFF Block 0 ( FFFh) not protected from table reads executed in other blocks ON Block 0 ( FFFh) protected from table reads executed in other blocks EBTR1 = Table Read Protection bit OFF Block 1 ( FFF) not protected from table reads executed in other blocks ON Block 1 ( FFF) protected from table reads executed in other blocks EBTR2 = Table Read Protection bit OFF Block 2 ( FFFh) not protected from table reads executed in other blocks ON Block 2 ( FFFh) protected from table reads executed in other blocks EBTR3 = Table Read Protection bit OFF Block 3 ( FFFh) not protected from table reads executed in other blocks ON Block 3 ( FFFh) protected from table reads executed in other blocks Register: 0x30000D EBTRB = Boot Block Table Read Protection bit OFF Boot Block ( FFh) not protected from table reads executed in other blocks ON Boot Block ( FFh) not protected from table reads executed in other blocks Register: 0x Register: 0x200001

6 6 z :21 Register: 0x Register: 0x Register: 0x Register: 0x Register: 0x Register: 0x200007