COSC345 Software Engineering. Make

Transcription

1 COSC345 Software Engineering Make

2 The build process Make When to use make How to use make Suffix rules makedepend Outline Warning: Make is different everywhere you go!

3 Build Process The build process can often: Be complex Rely on several different processes Be time-consuming Be difficult to remember defs.h command.h main.c kbd.c main.o kbd.o edit

4 Dependencies If a header changes then the source must be recompiled If command.h changes then recompile kbd.c relink edit Actually, we must rebuild: All files that include the header All executables dependant on the object code All libraries dependant on the object code All executables dependant on the library And all in the right order!

5 What Make Does We need some way of scripting the build process When changes are made: Only re-build the parts that are necessary Automatically work out which parts those are Make Manages the creation of output files from source files Uses a configuration file (makefile) to specify how Uses file time-stamps to determine what s out-of-date Make also: Enables those new to a project to build it without understanding the build process Enables the developers to build: Clean-up scripts Install scripts

6 When to use Make When the project has more than one file When the build process is more than just compile It reduces compile / debug cycle time When the build process is different on different machines When you expect to go-back to a project later And won t be able to remember how to build it In short always The time required to write a makefile is very small It saves time if you re going to compile more than once

7 Make Scripting Make uses a script to determine: Which files need rebuilding The order they should be rebuilt If you change only one thing then make will make changes only to files dependant on that change In a script (a makefile) you tell make How to execute a series of commands to make a target from sources What the target is dependant on Call your makefile either makefile or Makefile

8 Make Rules A makefile is made from a series of rules <target> : <dependency> <dependency> <command> <command> <target> is the name of the file to be built <dependency> is the name of a file needed to build it <command> is each command needed to create the target Commands are indented by one tab A rule describes how and when to perform an action Unless specified otherwise make builds only the first target

9 Sample Makefile edit : main.o kbd.o cc -o edit main.o kbd.o main.o : main.c defs.h cc -c main.c kbd.o : kbd.c defs.h command.h cc -c kbd.c clean : rm edit main.o kbd.o In the rule: edit : main.o kbd.o cc -o edit main.o kbd.o The target is edit The dependents are main.o and kbd.o The command is cc -o edit main.o kbd.o Which will result in edit being built

10 What Make Does Read the makefile Generate a dependency graph for the first target Starting at the target For every dependent Target the dependent If any dependent is more recent then the target Execute the commands If any target doesn t exist Execute the commands To run make on Linux: make To run make on Windows: nmake

11 In the example: Dependency Graph If any of the.h or.c files is touched then edit is rebuilt edit : main.o kbd.o cc -o edit main.o kbd.o main.o : main.c defs.h cc -c main.c kbd.o : kbd.c defs.h command.h cc -c kbd.c clean : rm edit main.o kbd.o main.c main.o defs.h edit kbd.c kbd.o command.h

12 Commands Make will execute one or more commands specified: Each on separate line Without blank lines between them clean : rm edit rm main.o kbd.o Make does not execute commands directly, it calls a (configurable) shell to execute them If a command returns an error (non-zero) then make exits This stops the build process at the first error Commands are not echoed to the console (silent) - the return code is ignored (can t produce an error)

13 Macros / Inference Rules Macros can be defined objects = main.o kbd.o And used edit : $(objects) cc -o edit $(objects) So changes only need to be made in one place Some rules are inferred main.o : defs.h kbd.o : defs.h command.h Make knows how to make.c files into.o files

14 Inference Rules main.o is made from main.c & defs.h by an inference rule: $(CC) -c $(CFLAGS) main.c Inference rules can be specified in the makefile <.from><.to>: <command> <command> Example.c.o: $(CC) -c $(CFLAGS) $< Make must be told about inference rules.suffixes: #Clear the suffix list.suffixes:.c.o #Append to the suffix list

15 Predefined Macros Make has many built in default macros: For compilers it includes For inference rules it includes: Macro Definition Compiler Flags CC CXX CFLAGS CXXFLAGS Current target's full name $< Dependent file with a later timestamp than the current target $? All dependents with a later timestamp than the current target $* Current target's path and base name minus file extension $+ All dependents of the current target As well as the environment variables

16 Other Rules Multiple targets for a dependency main.o kdb.o : defs.h kbd.o : command.h Targets built by multiple commands (::) libaspt.a :: kbd.o ar -rv libaspt.a kbd.o libaspt.a :: another.o ar -rv libaspt.a another.o Makefiles can include other makefiles include another.mak # at the beginning of a line is a comment

17 Dependencies The dependencies must be kept up-to-date Every new header file included must be accounted for This is time consuming and prone to error Tools exist to build the dependencies makedepend mkdep And others too For more on makedepend (on Linux) try man makedepend

18 Make-like Tools Many IDEs have make-like tools Visual Studio Xcode Many IDEs require their build files to debug Visual Studio does not Xcode (essentially) does Cmake Reads CMakeLists.txt and converts into different formats Visual Studio, Xcode, Make, etc. Cmake is a bit esoteric but it is cross-platform Linux, Mac, Windows, etc.

19 GNU make References NMAKE reference Cmake