Memory Optimization for OpenCL on Intel FPGAs Exercise Manual
|
|
- Junior Williamson
- 5 years ago
- Views:
Transcription
1 Memory Optimization for OpenCL on Intel FPGAs Exercise Manual Software Requirements that cannot be adjusted: Intel FPGA SDK for OpenCL version 17.1 Software Requirements that can be adjusted: Operation System: CentOS 6.9 (Linux) Use the link below to download the design files for the exercise: *OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission of Khronos
2 In this exercise, you will practice using a few common techniques to improve local memory architecture in a component. We will look at how to bank explicitly on specified bits, how to guide the compiler to build a stall-free memory architecture, and how to merge memory. Step 1. Memory Banking and Coalescing Unzip the lab files using the command unzip lab.zip Change to the lab/ directory by typing cd lab Open the file in opencl_init.sh and change the paths to paths in your system to the Intel FPGA SDK for OpenCL installation directory Set up your environment for the lab by typing source opencl_init.sh Open bankbits.cl in a text editor This is a simple memory example, we have two local memory arrays, local_a and local_b. Based on the values of the input arguments, we will perform unrolled reads and writes. For the first loop, we would like local_a to be able to store 8 values at a time stall-free (because the loop is unrolled 8 times). For the second loop, we would 2
3 like local_a to be able to load 4 values at a time stall-free, and local_b to store 4 at a time. (The third loop is there to prevent optimizations from not using a result.) Since upperdim is constant for the duration of each of the loops, we should be able to bank the memory so that everything can be stall free. Many times, the compiler can figure out to do that. However, with complicated coding constructs, it cannot always figure out the correct structure. Compile bankbits into an object file by running the following command in the terminal: aoc -c -board=a10gx bankbits.cl When the compile has finished, open the HTML report by typing the following command (or use any web browser): firefox bankbits/reports/report.html Note the resource consumption of the Kernel System on the Summary page ALUTs FFs RAMs Go to Loop analysis What s the II of the component invocation? You see here that the II is ~1. The ~ in the II represents that the number is approximate because of stallable loads and stores. This is one case where the stallable loads and stores will cause you to have a much longer run time than you would have predicted using II alone. This is why it is important to examine all sections of the HTML report. Go to the System Viewer section of the HTML report. Here you can immediately see all of the loads and stores happening. There are 8 stores from the from the first loop, and 4 loads and stores from the second loop. 3
4 11. Hover over the local_b memory. You can see that the compiler ran this memory at 2x clock giving it 4 ports. It attempted to bank the memory on the lower bits but did not discover the optimal structure, and was not able to coalesce or replicate. Because there are 8 simultaneous access aggregating on 4 ports, these accesses are stallable and need to be arbitrated 4
5 12. Switch to the Kernel Memory Viewer section of the HTML report and click on Bank 0 of local_b in the Memory list. Here again you see the 8 accesses aggregating 8 ports with arbitration at every port. 5
6 Step 2. Change the kernel to optimize banking Open bankbits.cl in a text editor if it is not already open. Currently, the upper dimension of the arrays are indexed by upperdim+i. The intention of upperdim was to provide the upper bits of the address. However, the addition operation does not provide enough information to the compiler to know that upperdim will always be a multiple of 16. Mask the lower 4 bits of upperdim everywhere it is used. Also mask bits 31 to 9, leaving only bits 8 through 5 unmasked. Use the & operation with the number 0x000001F0. Save your modified kernel as bankbits_mask.cl Compile the kernel using aoc -c -board=a10gx bankbits_mask.cl. Open the HTML report by typing firefox bankbits_mask/reports/report.html Go to the System Viewer section of the report. You can quickly see by all of the red nodes that the compiler has not discovered the optimal banking structure Go back to the text editor and figure out the bits that would provide the optimal banking structure and use the attribute bankbits to specify that to the compiler. Hint: The only address bits where the 8 access differ is based on the loop variable i. The lowest dimention of the a array [2000] uses 11 bits. The LSB bit is bit 0. 3 bits are needed to provide 8 banks, which is the amount of banks we want. Save the modified kernel as bankbits_attribute.cl 6
7 Compile the kernel using the command below aoc -c -board=a10gx bankbits_attribute.cl Open the HTML report Go to the component viewer and hover over the local memory As you can see from this report, we have 8 banks but because we are not banking on the optimal bits, the local memory is still stallable. Go to an Area Report section of the HTML report. Note the resource consumption of the Kernel System. ALUTs FFs RAMs There is another recommendation that we have not followed yet. It is recommended to have the indices as powers of 2 to make it easier for the compiler to bank. Go back to the text editor and make the lower index of the local arrays a power of 2. Since it is already close to a power of 2, this will not add that many resources. Save your modified kernel as bankbits_powerof2.cl Compile the kernel into an object file. 7
8 15. Open the HTML report and go to the System Viewer section You can tell from the lack of red that the compiler figured out the optimal banking configuration and produced stall free nodes. Go to an Area Report section of the HTML report. Note the resource consumption of the Kernel System. ALUTs FFs RAMs Note the resource savings from an optimal banking structure. Stall-free nodes mean no arbitration is needed, and thus no resources are needed to build up arbiters and the control logic associated with stalls. Open the file bankbits_mask.cl again. You learned in class that the compiler prefers to bank on the lower dimension bits. In the bankbits_mask.cl file, turn the indices around every place they occur. Now, the variable i which we want to bank on is in the lower index. Save the file as bitbanks_turnaround.cl and compile it using the command shown below. aoc -c -board=a10gx bitbanks_turnaround.cl 8
9 Open the HTML report using the command firefox bitbanks_turnarond/reports/report.html Switch to the System Viewer section of the report. Using the lower indices allowed the tools to figure out a banking structure on its own, which is even more optimal than the one it finally chose with the upper bits. Try swapping indices first before all of the other things in real designs. Exercise Summary Practiced using bank attributes and coding styles for the compiler to generate the optimal memory architecture. Learned what technique is most effective for inferring banking. END OF EXERCISE 5 9
10 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 10
Intel Quartus Prime Software Download and Installation Quick Start Guide
Intel Quartus Prime Software Download and Installation Quick Start Guide Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus, and Stratix
More informationQuick Start Guide for Intel FPGA Development Tools on the Nimbix Cloud
Quick Start Guide for Intel FPGA Development Tools on the Nimbix Cloud Updated for Intel Quartus Prime Design Suite: 17.0.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationIntel Stratix 10 H-Tile PCIe Link Hardware Validation
Intel Stratix 10 H-Tile PCIe Link Hardware Validation Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel Stratix 10 H-Tile PCIe* Link Hardware Validation... 3 1.1.
More informationQuick Start Guide for Intel FPGA Development Tools on the Microsoft* Azure* Platform
Quick Start Guide for Intel FPGA Development Tools on the Microsoft* Azure* Platform Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents
More informationIntel High Level Synthesis Compiler
Intel High Level Synthesis Compiler User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1....3 2. Overview of the
More informationAN 834: Developing for the Intel HLS Compiler with an IDE
AN 834: Developing for the Intel HLS Compiler with an IDE Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Developing for the Intel HLS Compiler with an Eclipse* IDE...
More informationIntel Acceleration Stack for Intel Xeon CPU with FPGAs 1.0 Errata
Intel Acceleration Stack for Intel Xeon CPU with FPGAs 1.0 Errata Updated for Intel Acceleration Stack for Intel Xeon CPU with FPGAs: 1.0 Production Subscribe Send Feedback Latest document on the web:
More informationIntel Arria 10 Native Floating- Point DSP Intel FPGA IP User Guide
Intel Arria 10 Native Floating- Point DSP Intel FPGA IP User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1...3 1.1 Parameterizing the Intel Arria 10 Native Floating-Point
More informationIntel Stratix 10 H-tile Hard IP for Ethernet Design Example User Guide
Intel Stratix 10 H-tile Hard IP for Ethernet Design Example User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationIntel Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide
Intel Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel Stratix 10 LAB and Overview... 3 2 HyperFlex
More informationHigh Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example User Guide
High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Updated for Intel Quartus Prime Design Suite: 18.1.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. High Bandwidth
More informationIntel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim
Intel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim AN-828 2017.10.02 Subscribe Send Feedback Contents Contents 1... 3 1.1 Conventions...3 1.2 Glossary...3 1.3 Introduction...3 1.4 Design...
More informationIntel High Level Synthesis Compiler
Intel High Level Synthesis Compiler Best Practices Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel HLS Compiler
More informationInterlaken IP Core (2nd Generation) Design Example User Guide
Interlaken IP Core (2nd Generation) Design Example User Guide UG-20051 2017.09.19 Subscribe Send Feedback Contents Contents 1 Quick Start Guide... 3 1.1 Directory Structure... 4 1.2 Design Components...
More informationCustomizable Flash Programmer User Guide
Customizable Flash Programmer User Guide Subscribe Latest document on the web: PDF HTML Contents Contents 1. Customizable Flash Programmer Overview... 3 1.1. Device Family Support...3 1.2. Software Support...
More informationIntel HLS Compiler: Fast Design, Coding, and Hardware
white paper Intel HLS Compiler Intel HLS Compiler: Fast Design, Coding, and Hardware The Modern FPGA Workflow Authors Melissa Sussmann HLS Product Manager Intel Corporation Tom Hill OpenCL Product Manager
More informationIntel Cyclone 10 External Memory Interfaces IP Design Example User Guide
Intel Cyclone 10 External Memory Interfaces IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationIntel FPGA SDK for OpenCL
Intel FPGA SDK for OpenCL Best Practices Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Introduction... 5 1.1
More informationAN 807: Configuring the Intel Arria 10 GX FPGA Development Kit for the Intel FPGA SDK for OpenCL
AN 807: Configuring the Intel Arria 10 GX FPGA Development Kit for the Intel FPGA SDK for OpenCL Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents Configuring the Intel Arria
More informationIntel Quartus Prime Pro Edition Software and Device Support Release Notes
Intel Quartus Prime Pro Edition Software and Device Support Release Notes RN-01082-17.0.0 2017.05.08 Subscribe Send Feedback Contents Contents 1 Version 17.0... 3 1.1 New Features and Enhancements...3
More informationAN 464: DFT/IDFT Reference Design
Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents About the DFT/IDFT Reference Design... 3 Functional Description for the DFT/IDFT Reference Design... 4 Parameters for the
More informationExternal Memory Interfaces Intel Arria 10 FPGA IP Design Example User Guide
External Memory Interfaces Intel Arria 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationIntel Acceleration Stack for Intel Xeon CPU with FPGAs Version 1.2 Release Notes
Intel Acceleration Stack for Intel Xeon CPU with FPGAs Version 1.2 Updated for Intel Acceleration Stack for Intel Xeon CPU with FPGAs: 1.2 Subscribe Latest document on the web: PDF HTML Contents Contents
More informationIntel Stratix 10 Low Latency 40G Ethernet Design Example User Guide
Intel Stratix 10 Low Latency 40G Ethernet Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Quick Start Guide...
More informationNios II Embedded Design Suite Release Notes
Nios II Embedded Design Suite Release Notes Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1...3 1.1 Product Revision History... 3 1.2 Nios II EDS v15.0 Updates...4 1.3
More informationTiming Analyzer Quick-Start Tutorial
Timing Analyzer Quick-Start Tutorial Intel Quartus Prime Pro Edition Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents Timing
More informationSerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices
SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Stratix 10 ES Editions Subscribe Send Feedback Latest document
More informationIntel Quartus Prime Pro Edition
Intel Quartus Prime Pro Edition Version 18.1 Software and Device Support Release Notes Subscribe Latest document on the web: PDF HTML Contents Contents 1. Intel Quartus Prime Pro Edition Version 18.1 Software
More informationIntel FPGA Temperature Sensor IP Core User Guide
Intel FPGA Temperature Sensor IP Core User Guide UG-01074 2017.09.14 Subscribe Send Feedback Contents Contents... 3 Intel FPGA Temperature Sensor Features...3 Intel FPGA Temperature Sensor Functional Description...
More informationAN 839: Design Block Reuse Tutorial
AN 839: Design Block Reuse Tutorial for Intel Arria 10 FPGA Development Board Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationIntel Quartus Prime Pro Edition Software and Device Support Release Notes
Intel Quartus Prime Pro Edition Software and Device Support Release Notes Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Version 18.0... 3 1.1. New Features and Enhancements...3
More informationSimulating the ASMI Block in Your Design
2015.08.03 AN-720 Subscribe Supported Devices Overview You can simulate the ASMI block in your design for the following devices: Arria V, Arria V GZ, Arria 10 Cyclone V Stratix V In the Quartus II software,
More informationAN 831: Intel FPGA SDK for OpenCL
AN 831: Intel FPGA SDK for OpenCL Host Pipelined Multithread Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA SDK for OpenCL Host Pipelined Multithread...3 1.1
More informationIntel Stratix 10 External Memory Interfaces IP Design Example User Guide
Intel Stratix 10 External Memory Interfaces IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationNios II Custom Instruction User Guide
Nios II Custom Instruction User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Nios II Custom Instruction Overview...4 1.1 Custom Instruction Implementation... 4
More informationAN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board
AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents Partially Reconfiguring
More informationIntel FPGA SDK for OpenCL Standard Edition
Intel FPGA SDK for OpenCL Standard Edition Programming Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel FPGA
More informationIntel FPGA SDK for OpenCL Pro Edition
Intel FPGA SDK for OpenCL Pro Edition Programming Guide Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Intel FPGA SDK for OpenCL
More informationIntel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide
Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide Updated for Intel Acceleration Stack: 1.0 Production Subscribe Send Feedback Latest document on the web: PDF
More informationDSP Development Kit, Stratix II Edition
DSP Development Kit, Stratix II Edition August 2005, Development Kit version 1.1.0 Errata Sheet This document addresses known errata and documentation changes the DSP Development Kit, Stratix II Edition
More information25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. 25G
More informationAN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board
AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents
More informationSerialLite III Streaming IP Core Design Example User Guide for Intel Arria 10 Devices
IP Core Design Example User Guide for Intel Arria 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Quick Start
More informationLow Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationIntel FPGA SDK for OpenCL
Intel FPGA SDK for OpenCL Programming Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA SDK for OpenCL
More informationPCI Express Multi-Channel DMA Interface
2014.12.15 UG-01160 Subscribe The PCI Express DMA Multi-Channel Controller Example Design provides multi-channel support for the Stratix V Avalon Memory-Mapped (Avalon-MM) DMA for PCI Express IP Core.
More informationAltera ASMI Parallel II IP Core User Guide
Altera ASMI Parallel II IP Core User Guide UG-20068 2017.05.08 Last updated for Intel Quartus Prime Design Suite: 17.0 Subscribe Send Feedback Contents Contents 1... 3 1.1 Ports...4 1.2 Parameters... 5
More informationNios II Performance Benchmarks
Subscribe Performance Benchmarks Overview This datasheet lists the performance and logic element (LE) usage for the Nios II Classic and Nios II Gen2 soft processor, and peripherals. Nios II is configurable
More informationSimplify Software Integration for FPGA Accelerators with OPAE
white paper Intel FPGA Simplify Software Integration for FPGA Accelerators with OPAE Cross-Platform FPGA Programming Layer for Application Developers Authors Enno Luebbers Senior Software Engineer Intel
More informationIntel Stratix 10 Analog to Digital Converter User Guide
Intel Stratix 10 Analog to Digital Converter User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel Stratix
More informationIntel MAX 10 User Flash Memory User Guide
Intel MAX 10 User Flash Memory User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel MAX 10 User Flash Memory
More informationIntel FPGA USB Download Cable User Guide
Intel FPGA USB Download Cable User Guide Subscribe Latest document on the web: PDF HTML Contents Contents 1. Introduction to Intel FPGA Download Cable...3 1.1. Intel FPGA Download Cable Revision... 3 1.2.
More informationASMI Parallel II Intel FPGA IP Core User Guide
ASMI Parallel II Intel FPGA IP Core User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1.... 3 1.1. Ports...4 1.2.
More informationPCI Express*: Migrating to Intel Stratix 10 Devices for the Avalon Streaming Interface
PCI Express*: Migrating to Intel Stratix 10 Devices for the Avalon Streaming Interface AN791 2017.05.08 Last updated for Intel Quartus Prime Design Suite: Quartus Prime Pro v17.1 Stratix 10 Editions Subscribe
More informationGeneric Serial Flash Interface Intel FPGA IP Core User Guide
Generic Serial Flash Interface Intel FPGA IP Core User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Generic
More informationIntel Quartus Prime Pro Edition Software and Device Support Release Notes
Intel Quartus Prime Pro Edition Software and Device Support Release Notes Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Version 17.1... 3 1.1 New Features and Enhancements...3
More informationAN 818: Static Update Partial Reconfiguration Tutorial
AN 818: Static Update Partial Reconfiguration Tutorial for Intel Stratix 10 GX Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Static
More informationIntel Quartus Prime Standard Edition Software and Device Support Release Notes
Intel Quartus Prime Standard Edition Software and Device Support Release Notes RN-01080-.0 205.08 Subscribe Send Feedback Contents Contents 1 Intel Quartus Prime Standard Edition Software and Device Support
More informationAN 818: Static Update Partial Reconfiguration Tutorial
AN 818: Static Update Partial Reconfiguration Tutorial for Intel Stratix 10 GX FPGA Development Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF
More informationIntel FPGA Voltage Sensor IP Core User Guide
Intel FPGA Voltage Sensor IP Core User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA Voltage Sensor
More informationAN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/ LVCMOS I/O Systems
AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/ LVCMOS I/O Systems Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents Interfacing Intel FPGA Devices with 3.3/3.0/2.5
More informationMailbox Client Intel Stratix 10 FPGA IP Core User Guide
Mailbox Client Intel Stratix 10 FPGA IP Core User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1.1 Feature Description...3 1.2 Command & Error Code...4 1.2.1 Commands...
More informationRemote Update Intel FPGA IP User Guide
Remote Update Intel FPGA IP User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Remote Update Intel FPGA IP User Guide... 3
More informationIntel SoC FPGA Embedded Development Suite User Guide
Intel SoC FPGA Embedded Development Suite User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Introduction to
More informationAN 826: Hierarchical Partial Reconfiguration Tutorial for Stratix 10 GX FPGA Development Board
AN 826: Hierarchical Partial Reconfiguration Tutorial for Stratix 10 GX FPGA Development Board Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF
More informationH-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
H-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationLow Latency 100G Ethernet Design Example User Guide
Low Latency 100G Ethernet Design Example User Guide Updated for Intel Quartus Prime Design Suite: 16.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Quick Start Guide...
More informationActive Serial Memory Interface
Active Serial Memory Interface October 2002, Version 1.0 Data Sheet Introduction Altera Cyclone TM devices can be configured in active serial configuration mode. This mode reads a configuration bitstream
More informationAN 797: Partially Reconfiguring a Design on Intel Arria 10 GX FPGA Development Board
AN 797: Partially Reconfiguring a Design on Intel Arria 10 GX FPGA Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents Partially Reconfiguring
More informationAN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design
AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Subscribe Latest document on the web: PDF HTML Contents Contents 1. Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference
More informationAN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface
AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 RapidIO II Reference Design for Avalon -ST Pass-Through
More informationAN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design
AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA Triple-Speed Ethernet and On-Board
More informationStratix 10 Serial Flash Mailbox Client Intel FPGA IP Core User Guide
Stratix 10 Serial Flash Mailbox Client Intel FPGA IP Core User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents...3
More informationLow Latency 40G Ethernet Example Design User Guide
Low Latency 40G Ethernet Example Design User Guide Subscribe UG-20025 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents Quick Start Guide...1-1 Directory Structure... 1-2 Design Components...
More informationApplying the Benefits of Network on a Chip Architecture to FPGA System Design
white paper Intel FPGA Applying the Benefits of on a Chip Architecture to FPGA System Design Authors Kent Orthner Senior Manager, Software and IP Intel Corporation Table of Contents Abstract...1 Introduction...1
More informationIntel Stratix 10 Variable Precision DSP Blocks User Guide
Intel Stratix 10 Variable Precision DSP Blocks User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel Stratix
More informationDisassemble the machine code present in any memory region. Single step through each assembly language instruction in the Nios II application.
Nios II Debug Client This tutorial presents an introduction to the Nios II Debug Client, which is used to compile, assemble, download and debug programs for Altera s Nios II processor. This tutorial presents
More informationAN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines
AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines AN-756 2017.05.08 Subscribe Send Feedback Contents Contents 1...3 1.1 Implementing the Altera PHYLite Design... 3 1.1.1 Parameter
More informationIntel Quartus Prime Standard Edition Software and Device Support Release Notes
Intel Quartus Prime Standard Edition Software and Device Support Release Notes Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel Quartus Prime Standard Edition Software
More informationIntel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe* Design Example User Guide
Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe* Design Example User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Quick Start Guide... 3 1.1
More information10. Introduction to UniPHY IP
10. Introduction to Uni IP November 2012 EMI_RM_008-2.1 EMI_RM_008-2.1 The Altera,, and LP SDRAM controllers with Uni, QDR II and QDR II+ SRAM controllers with Uni, RLDRAM II controller with Uni, and RLDRAM
More informationEarly Power Estimator for Intel Stratix 10 FPGAs User Guide
Early Power Estimator for Intel Stratix 10 FPGAs User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Overview of the Early Power Estimator for Intel Stratix 10 Devices...3
More informationIntel FPGA USB Download Cable User Guide
Intel FPGA USB Download Cable User Guide UG-USB81204 2016.10.31 Subscribe Send Feedback Contents Contents 1 Introduction to USB Download Cable... 3 1.1 USB Download Cable Revision... 3 1.2 Supported Devices
More informationIntroduction to Simulation of VHDL Designs Using ModelSim Graphical Waveform Editor. 1 Introduction. For Quartus Prime 16.1
Introduction to Simulation of VHDL Designs Using ModelSim Graphical Waveform Editor For Quartus Prime 16.1 1 Introduction This tutorial provides an introduction to simulation of logic circuits using the
More informationDDR and DDR2 SDRAM Controller Compiler User Guide
DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Operations Part Number Compiler Version: 8.1 Document Date: November 2008 Copyright 2008 Altera
More informationUTOPIA Level 2 Slave MegaCore Function
UTOPIA Level 2 Slave MegaCore Function October 2005, Version 2.5.0 Release Notes These release notes for the UTOPIA Level 2 Slave MegaCore function contain the following information: System Requirements
More informationIntel MAX 10 Embedded Memory User Guide
Intel MAX 10 Embedded Memory User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel MAX 10 Embedded Memory Overview...4 2. Intel MAX 10 Embedded Memory Architecture
More informationIntel Arria 10 and Intel Cyclone 10 Avalon-ST Hard IP for PCIe* Design Example User Guide
Intel Arria 10 and Intel Cyclone 10 Avalon-ST Hard IP for PCIe* Design Example User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Quick Start Guide... 3 1.1 Directory
More informationAN 829: PCI Express* Avalon -MM DMA Reference Design
AN 829: PCI Express* Avalon -MM DMA Reference Design Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Latest document on the web: PDF HTML Contents Contents 1....3 1.1. Introduction...3 1.1.1.
More information4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices
January 2011 HIV51004-2.2 4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices HIV51004-2.2 This chapter describes TriMatrix memory blocks, modes, features, and design considerations in HardCopy
More informationMailbox Client Intel Stratix 10 FPGA IP Core User Guide
Mailbox Client Intel Stratix 10 FPGA IP Core User Guide Subscribe Latest document on the web: PDF HTML Contents Contents 1.1. Feature Description...3 1.2. s and Error Codes...4 1.2.1. s... 5 1.2.2. Error
More informationBoard Update Portal based on Nios II Processor with EPCQ (Arria 10 GX FPGA Development Kit)
Board Update Portal based on Nios II Processor with EPCQ (Arria 10 GX FPGA Development Kit) Date: 1 December 2016 Revision:1.0 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY,
More informationEFEC20 IP Core. Features
EFEC20 IP Core DS-1034-1.2 Data Sheet The Altera 20% Enhanced Forward Error Correction (EFEC20) IP core includes a highperformance encoder and decoder for Optical Transport Network (OTN) FEC applications.
More informationDDR & DDR2 SDRAM Controller
DDR & DDR2 SDRAM Controller October 2005, Compiler Version 3.3.0 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.0 contain the following information: System
More informationLeveraging the Intel HyperFlex FPGA Architecture in Intel Stratix 10 Devices to Achieve Maximum Power Reduction
white paper FPGA Leveraging the Intel HyperFlex FPGA Architecture in Intel Stratix 1 s to Achieve Maximum Reduction devices leverage the innovative Intel HyperFlex FPGA architecture to achieve power savings
More informationMAX 10 Embedded Memory User Guide
MAX 10 Embedded Memory User Guide UG-M10MEMORY 2017.02.21 Subscribe Send Feedback Contents Contents 1 MAX 10 Embedded Memory Overview... 4 2 MAX 10 Embedded Memory Architecture and Features... 5 2.1 MAX
More informationEthernet Link Inspector User Guide v3.0 for Intel Stratix 10 Devices
Ethernet Link Inspector User Guide v3.0 for Intel Stratix 10 Devices Send Feedback Contents Contents 1. Overview of the Ethernet Link Inspector for Intel Stratix 10 Devices... 3 1.1. Features...3 1.1.1.
More information8. Introduction to UniPHY IP
8. Introduction to Uni IP November 2011 EMI_RM_008-1.1 EMI_RM_008-1.1 The Altera and SDRAM controllers with Uni, QDR II and QDR II+ SRAM controllers with Uni, and RLDRAM II controller with Uni provide
More informationSDI II Intel FPGA IP User Guide
Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. SDI II Intel FPGA IP Core Quick Reference... 4 2. SDI II Intel FPGA IP Core Overview...6
More informationSystem Debugging Tools Overview
9 QII53027 Subscribe About Altera System Debugging Tools The Altera system debugging tools help you verify your FPGA designs. As your product requirements continue to increase in complexity, the time you
More information