EFEC20 IP Core. Features
|
|
- Piers Reynolds
- 5 years ago
- Views:
Transcription
1 EFEC20 IP Core DS Data Sheet The Altera 20% Enhanced Forward Error Correction (EFEC20) IP core includes a highperformance encoder and decoder for Optical Transport Network (OTN) FEC applications. Bose-Chaudhuri-Hocquenghem (BCH) streaming turbo product codes correct errors in data transmitted across communication channels with various bit error rates (BERs). EFEC20 performs high-gain error correction with 20% overhead and is available for 100 gigabits per second (Gbps)/Optical Channel Transport Unit (OTU)4 data transmission. Features EFEC20 includes the following features: High-performance encoder and decoder for error detection and correction 100 Gbps OTN rate with 640 bit datapath width 20% overhead for Stratix IV and Stratix V devices Latency of < 32 µs Net electrical coding gain (NECG) of > 10.3 db Error statistic monitoring, including the following types: Corrected zeros and ones errors Corrected errors and uncorrectable errors 100 Gbps/OTU4 frame count 101 Innovation Drive San Jose, CA Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered May 2012 Altera Corporation Subscribe
2 Page 2 Architecture Architecture Figure 1 illustrates the system architecture of the EFEC20 IP core. Data from an incoming client is adapted to OTN before it is written to the OTN mapper. The data is encoded with redundant data at the FEC encoder before it is transmitted across the network. The redundant data is decoded at the FEC decoder and identified errors are corrected before the data is written to the OTN framer. The data is then adapted back to the original client. Figure 1. EFEC20 System Architecture Customer or Altera IP Altera IP Core Altera IP Core Customer or Altera IP Client Adaptation OTN Mapper OTN FEC Encoder OTN OTN FEC Decoder OTN Framer Client Adaptation Device Family Support Table 1. Altera IP Core Device Support Levels Table 1 defines the device support levels for Altera IP cores. FPGA Device Families Preliminary support The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution. Final support The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. HardCopy Device Families HardCopy Companion The IP core is verified with preliminary timing models for the HardCopy companion device. The IP core meets all functional requirements, but might still be undergoing timing analysis for the HardCopy device family. It can be used in production designs with caution. HardCopy Compilation The IP core is verified with final timing models for the HardCopy device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. Table 2 lists the level of support for EFEC20 in each of the Altera device families. Table 2. Device Family Support Device Family Stratix IV GT Stratix IV E/GX Stratix V E/GX/GS/GT All other device families Final Preliminary Preliminary Not available Support IP Core Verification Before releasing a version of the EFEC20 IP core, Altera runs comprehensive regression tests to verify its quality and correctness. EFEC20 IP Core May 2012 Altera Corporation
3 Performance and Resource Utilization Page 3 Performance and Resource Utilization Stratix IV devices use combinational adaptive look-up tables (ALUTs) and logic registers. Table 3 shows the typical performance for 100 Gbps EFEC20 on the Stratix IV GT (EP4S100G5H40I1(N)) device as reported by the Quartus II software. Table 3. Performance - EFEC20 on Stratix IV GT (1) Options ALUTS Logic Registers Decoder Memory (M9K) Memory (144K) f MAX (MHz) Encoder Decoder Note to Table 3: (1) Please contact Altera s OTN account manager at otn_info@altera.com for detailed performance information. Figure 2. EFEC20 Bit Error Rate Net Electrical Gain (NECG) Latency > 10.3 db < 32 µs Figure 2 shows the Input BER and Output BER of the EFEC20 in comparison to the International Telecommunication Union, Telecommunication Standardization Sector (ITU-T) G.709 standardized FEC application. Input Bit Error Rate 1.00E E E E E-05 Output Bit Error Rate 1.00E E E E E E-17 Altera EFEC20 G.709 FEC May 2012 Altera Corporation EFEC20 IP Core
4 Page 4 Port Listing Port Listing Table 4 lists the encoder input and output ports for connecting to the EFEC20 IP core. Table 4. Encoder I/O Port Listing Port Width I/O Port (Bits) Input sys_clk 1 Clock port. Input i_rst 1 Input i_enable_n 1 Input i_max_column_width 8 Input i_row 2 Input i_col 8 Description This reset port is expected to meet removal and recovery constraints for sys_clk. This is an asynchronous reset and is active high. Enable encoder and decoder port. This is a synchronous signal and is active low. This input signals the OTN column count to adjust for the various OTN overhead rates supported by this application. Input OTN frame row port. This is a Input OTN frame column port. This is a Input i_data_en 1 Input enable data port. This is a synchronous Input i_data 640 Input data port. Output o_row 2 Output o_col 8 Output OTN frame row port. This is a Output OTN frame column port. This is a Output o_data_en 1 Output enable data port. This is a synchronous Output o_data 640 Output data port. Table 5 lists the decoder input ports and output ports for connecting to the EFEC20 IP core. Table 5. Decoder I/O Port Listing (Part 1 of 2) Port Width I/O Port (Bits) Input sys_clk 1 Clock port. Input i_rst 1 Input i_enable_n 1 Input i_max_column_width 8 Input i_error_scrambler_en_n 1 Description This reset port is expected to meet removal and recovery constraints for sys_clk. This is an asynchronous reset and is active high. Enable encoder and decoder port. This is a synchronous signal and is active low. This input signals the OTN column count to adjust for the various OTN overhead rates supported by this application. This input enables error scrambling. This is a synchronous signal and is active low. EFEC20 IP Core May 2012 Altera Corporation
5 Port Listing Page 5 Table 5. Decoder I/O Port Listing (Part 2 of 2) I/O Port Input i_row 2 Input i_col 8 Document Revision History Table 6 shows the revision history for this document. Input OTN frame row port. This is a Input OTN frame column port. This is a Input i_data_en 1 Input enable data port. This is a synchronous Input i_data 640 Input data port. Input i_latch_counters 1 Output o_0s_fec_errors 32 Output o_1s_fec_errors 32 Output o_fec_errors 32 Output o_uncorrectables 32 Output o_otu4_frames 32 Output o_row 2 Output o_col 8 Port Width (Bits) Description This input controls performance latch counters. The input latch counter pulses to receive the value count from one latch to the next latch. This is a synchronous This output signals the number of zeros errors within the performance interval controlled by i_latch_counters. This is a synchronous signal. This output signals the number of ones errors within the performance interval controlled by i_latch_counters. This is a synchronous signal. This output signals the total number of errors within the performance interval controlled by i_latch_counters. This is a synchronous signal. This output signals the number of uncorrectable RS codes. It is controlled by i_latch_counters Output OTU4 frames port. This is a synchronous signal and is controlled by i_latch_counters. Output OTN frame row port. This is a Output OTN frame column port. This is a Output o_data_en 1 Output enable data port. This is a synchronous Output o_data 640 Output data port. Table 6. Document Revision History Date Version Changes May Added otn_info@altera.com mailbox. March Updated NECG. February Initial release. May 2012 Altera Corporation EFEC20 IP Core
6 Page 6 Port Listing EFEC20 IP Core May 2012 Altera Corporation
OTU2 I.9 FEC IP Core (IP-OTU2EFECI9) Data Sheet
OTU2 I.9 FEC IP Core (IP-OTU2EFECI9) Data Sheet Revision 0.02 Release Date 2015-02-11 Document number . All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and ARRIA words
More informationOTU2 I.4 FEC IP Core (IP-OTU2EFECI4Z) Data Sheet
OTU2 I.4 FEC IP Core (IP-OTU2EFECI4Z) Data Sheet Revision 0.08 Release Date 2014-03-29 Document number TD0307 . All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
More information10. Introduction to UniPHY IP
10. Introduction to Uni IP November 2012 EMI_RM_008-2.1 EMI_RM_008-2.1 The Altera,, and LP SDRAM controllers with Uni, QDR II and QDR II+ SRAM controllers with Uni, RLDRAM II controller with Uni, and RLDRAM
More information8. Introduction to UniPHY IP
8. Introduction to Uni IP November 2011 EMI_RM_008-1.1 EMI_RM_008-1.1 The Altera and SDRAM controllers with Uni, QDR II and QDR II+ SRAM controllers with Uni, and RLDRAM II controller with Uni provide
More informationPCI Express Multi-Channel DMA Interface
2014.12.15 UG-01160 Subscribe The PCI Express DMA Multi-Channel Controller Example Design provides multi-channel support for the Stratix V Avalon Memory-Mapped (Avalon-MM) DMA for PCI Express IP Core.
More informationNios II Performance Benchmarks
Subscribe Performance Benchmarks Overview This datasheet lists the performance and logic element (LE) usage for the Nios II Classic and Nios II Gen2 soft processor, and peripherals. Nios II is configurable
More informationRecommended Protocol Configurations for Stratix IV GX FPGAs
Recommended Protocol s for Stratix IV GX FPGAs AN-577-3.0 Application Note The architecture of the Altera Stratix IV GX FPGA is designed to accommodate the widest range of protocol standards spread over
More informationSimulating the ASMI Block in Your Design
2015.08.03 AN-720 Subscribe Supported Devices Overview You can simulate the ASMI block in your design for the following devices: Arria V, Arria V GZ, Arria 10 Cyclone V Stratix V In the Quartus II software,
More information2.5G Reed-Solomon II MegaCore Function Reference Design
2.5G Reed-Solomon II MegaCore Function Reference Design AN-642-1.0 Application Note The Altera 2.5G Reed-Solomon (RS) II MegaCore function reference design demonstrates a basic application of the Reed-Solomon
More informationMAX 10 User Flash Memory User Guide
MAX 10 User Flash Memory User Guide Subscribe Last updated for Quartus Prime Design Suite: 16.0 UG-M10UFM 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents MAX 10 User Flash Memory
More informationFFT MegaCore Function User Guide
FFT MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Version: 11.0 Document Date: May 2011 Copyright 2011 Altera Corporation. All rights reserved. Altera, The
More informationImplementing 9.8G CPRI in Arria V GT and ST FPGAs
03..06 AN 686 Subscribe This application note describes the implementation of 9.8304 Gbps Common Public Radio Interface (CPRI) using the Arria V GT and Arria V ST FPGA transceivers. The hard physical coding
More information11. SEU Mitigation in Stratix IV Devices
11. SEU Mitigation in Stratix IV Devices February 2011 SIV51011-3.2 SIV51011-3.2 This chapter describes how to use the error detection cyclical redundancy check (CRC) feature when a Stratix IV device is
More informationErrata Sheet for Cyclone IV Devices
Errata Sheet for Cyclone IV Devices ES-01027-2.3 Errata Sheet This errata sheet provides updated information on known device issues affecting Cyclone IV devices. Table 1 lists specific Cyclone IV issues,
More information100G Interlaken MegaCore Function User Guide
00G Interlaken MegaCore Function User Guide Subscribe UG-028 05.06.203 0 Innovation Drive San Jose, CA 9534 www.altera.com TOC-2 00G Interlaken MegaCore Function User Guide Contents About This MegaCore
More informationArria 10 Transceiver PHY User Guide
Arria 10 Transceiver PHY User Guide Subscribe UG-A10XCVR 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Arria 10 Transceiver PHY User Guide Contents Arria 10 Transceiver PHY Overview...1-1
More informationTable 1 shows the issues that affect the FIR Compiler v7.1.
May 2007, Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the Altera, v7.1. Errata are functional defects or errors, which may cause an Altera MegaCore function
More information4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices
January 2011 HIV51004-2.2 4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices HIV51004-2.2 This chapter describes TriMatrix memory blocks, modes, features, and design considerations in HardCopy
More informationDDR and DDR2 SDRAM Controller Compiler User Guide
DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Operations Part Number Compiler Version: 8.1 Document Date: November 2008 Copyright 2008 Altera
More informationDDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler May 2006, Compiler Version 3.3.1 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 3.3.1.
More informationDSP Development Kit, Stratix II Edition
DSP Development Kit, Stratix II Edition August 2005, Development Kit version 1.1.0 Errata Sheet This document addresses known errata and documentation changes the DSP Development Kit, Stratix II Edition
More informationRapidIO MegaCore Function
March 2007, MegaCore Function Version 3.1.1 Errata Sheet This document addresses known errata and documentation issues for the Altera RapidIO MegaCore function version 3.1.1. Errata are functional defects
More informationReal-Time ISP and ISP Clamp for Altera CPLDs
Real-Time ISP and ISP Clamp for Altera CPLDs AN-630-1.0 Application Note This application note describes the real-time in-system programmability (ISP) and ISP Clamp programming modes and their usage in
More informationIntel Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide
Intel Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel Stratix 10 LAB and Overview... 3 2 HyperFlex
More information3. ALTGX_RECONFIG IP Core User Guide for Stratix IV Devices
July 2014 SIV53004-2014.07.09 3. ALTGX_RECONFIG IP Core User Guide for Stratix IV Devices SIV53004-2014.07.09 This document describes how to define and instantiate the ALTGX_RECONFIG IP core using the
More information4K Format Conversion Reference Design
4K Format Conversion Reference Design AN-646 Application Note This application note describes a 4K format conversion reference design. 4K resolution is the next major enhancement in video because of the
More informationQuartus II Software Version 11.0 SP1 Device Support
Quartus II Software Version 11.0 SP1 Device Support RN-01066 Release Notes This document provides late-breaking information about device support in the Altera Quartus II software version 11.0 SP1. For
More informationUTOPIA Level 2 Slave MegaCore Function
UTOPIA Level 2 Slave MegaCore Function October 2005, Version 2.5.0 Release Notes These release notes for the UTOPIA Level 2 Slave MegaCore function contain the following information: System Requirements
More informationAltera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
2015.05.04 Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide UG-01155 Subscribe The Altera IOPLL megafunction IP core allows you to configure the settings of Arria 10 I/O PLL. Altera IOPLL
More informationE3 Mapper MegaCore Function (E3MAP)
MegaCore Function (E3MAP) March 9, 2001; ver. 1.0 Data Sheet Features Easy-to-use MegaWizard Plug-In generates MegaCore variants Quartus TM II software and OpenCore TM feature allow place-androute, and
More informationALTDQ_DQS2 Megafunction User Guide
ALTDQ_DQS2 Megafunction ALTDQ_DQS2 Megafunction 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01089-2.2 Feedback Subscribe 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE,
More informationIntel MAX 10 User Flash Memory User Guide
Intel MAX 10 User Flash Memory User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel MAX 10 User Flash Memory
More informationUsing the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices Subscribe Feedback The Altera Transceiver Reconfiguration Controller dynamically reconfigures
More informationSystem Debugging Tools Overview
9 QII53027 Subscribe About Altera System Debugging Tools The Altera system debugging tools help you verify your FPGA designs. As your product requirements continue to increase in complexity, the time you
More information9. SEU Mitigation in Cyclone IV Devices
9. SEU Mitigation in Cyclone IV Devices May 2013 CYIV-51009-1.3 CYIV-51009-1.3 This chapter describes the cyclical redundancy check (CRC) error detection feature in user mode and how to recover from soft
More informationDDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler march 2007, Compiler Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 7.0.
More informationWhite Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices
Introduction White Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices One of the challenges faced by engineers designing communications equipment is that memory devices
More informationDDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler August 2007, Compiler Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version
More informationWhite Paper. Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core. Introduction. Parameters & Ports
White Paper Introduction Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core The floating-point fast fourier transform (FFT) processor calculates FFTs with IEEE 754 single precision (1
More information9. Hot Socketing and Power-On Reset in Stratix IV Devices
February 2011 SIV51009-3.2 9. Hot Socketing and Power-On Reset in Stratix IV Devices SIV51009-3.2 This chapter describes hot-socketing specifications, power-on reset (POR) requirements, and their implementation
More informationRapidIO MegaCore Function
March 2007, MegaCore Function Version 3.1.0 Errata Sheet This document addresses known errata and documentation issues for the Altera RapidIO MegaCore function version 3.1.0. Errata are functional defects
More informationVideo and Image Processing Suite
Video and Image Processing Suite December 2006, Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the MegaCore functions in the Video and Image Processing Suite,
More informationDynamic Reconfiguration of PMA Controls in Stratix V Devices
Dynamic Reconfiguration of PMA Controls in Stratix V Devices AN-645-1.0 Application Note This application note describes how to use the transceiver reconfiguration controller to dynamically reconfigure
More information24K FFT for 3GPP LTE RACH Detection
24K FFT for GPP LTE RACH Detection ovember 2008, version 1.0 Application ote 515 Introduction In GPP Long Term Evolution (LTE), the user equipment (UE) transmits a random access channel (RACH) on the uplink
More informationDDR & DDR2 SDRAM Controller
DDR & DDR2 SDRAM Controller December 2005, Compiler Version 3.3.1 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.1 contain the following information: System
More informationPowerPlay Early Power Estimator User Guide
PowerPlay Early Power Estimator 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01070-7.1 Feedback Subscribe 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX,
More informationDDR & DDR2 SDRAM Controller
DDR & DDR2 SDRAM Controller October 2005, Compiler Version 3.3.0 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.0 contain the following information: System
More informationAN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices
AN 610: Implementing Deterministic Latency for CPRI and OBSAI Protocols in Altera Devices July 2010 AN-610-1.0 This application note describes how to implement deterministic latency for Common Public Radio
More informationQuad-Serial Configuration (EPCQ) Devices Datasheet
2016.05.30 CF52012 Subscribe This datasheet describes quad-serial configuration (EPCQ) devices. EPCQ is an in-system programmable NOR flash memory. Supported Devices Table 1: Supported Altera EPCQ Devices
More informationUsing the Nios Development Board Configuration Controller Reference Designs
Using the Nios Development Board Controller Reference Designs July 2006 - ver 1.1 Application Note 346 Introduction Many modern embedded systems utilize flash memory to store processor configuration information
More informationQDR II SRAM Board Design Guidelines
8 emi_dg_007 Subscribe The following topics provide guidelines for you to improve your system's signal integrity and layout guidelines to help successfully implement a QDR II or QDR II+ SRAM interface
More informationFPGAs Provide Reconfigurable DSP Solutions
FPGAs Provide Reconfigurable DSP Solutions Razak Mohammedali Product Marketing Engineer Altera Corporation DSP processors are widely used for implementing many DSP applications. Although DSP processors
More informationErrata Sheet for Cyclone V Devices
Errata Sheet for Cyclone V Devices ES-1035-2.5 Errata Sheet Table 1. Device Issues (Part 1 of 2) This errata sheet provides information about known issues affecting Cyclone V devices. Table 1 lists the
More informationAN 464: DFT/IDFT Reference Design
Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents About the DFT/IDFT Reference Design... 3 Functional Description for the DFT/IDFT Reference Design... 4 Parameters for the
More informationLow Latency 40G Ethernet Example Design User Guide
Low Latency 40G Ethernet Example Design User Guide Subscribe UG-20025 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents Quick Start Guide...1-1 Directory Structure... 1-2 Design Components...
More informationNIOS II Processor Booting Methods In MAX 10 Devices
2015.01.23 AN-730 Subscribe MAX 10 device is the first MAX device series which supports Nios II processor. Overview MAX 10 devices contain on-chip flash which segmented to two types: Configuration Flash
More informationLow Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Subscribe Last updated for Quartus Prime Design Suite: 16.0 UG-01172 101 Innovation Drive San Jose, CA 95134 www.altera.com
More informationConfiguration via Protocol (CvP) Implementation in Altera FPGAs User Guide
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide Subscribe UG-01101 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Configuration via Protocol (CvP) Implementation
More informationIntel Stratix 10 H-tile Hard IP for Ethernet Design Example User Guide
Intel Stratix 10 H-tile Hard IP for Ethernet Design Example User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationPCI Express Compiler. System Requirements. New Features & Enhancements
April 2006, Compiler Version 2.1.0 Release Notes These release notes for the PCI Express Compiler version 2.1.0 contain the following information: System Requirements New Features & Enhancements Errata
More informationIntel Arria 10 Native Floating- Point DSP Intel FPGA IP User Guide
Intel Arria 10 Native Floating- Point DSP Intel FPGA IP User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1...3 1.1 Parameterizing the Intel Arria 10 Native Floating-Point
More informationNios Soft Core Embedded Processor
Nios Soft Core Embedded Processor June 2000, ver. 1 Data Sheet Features... Preliminary Information Part of Altera s Excalibur TM embedded processor solutions, the Nios TM soft core embedded processor is
More informationRapidIO Physical Layer MegaCore Function
RapidIO Physical Layer MegaCore Function April 2005, MegaCore version 2.2.1 Errata Sheet Introduction This document addresses known errata and documentation changes for version 2.2.1 of the RapidIO Physical
More informationQuartus II Software Version 10.0 SP1 Device Support
Quartus II Software Version 10.0 SP1 Device Support RN-01057 Release Notes This document provides late-breaking information about device support in the 10.0 SP1 version of the Altera Quartus II software.
More informationPOS-PHY Level 4 MegaCore Function
POS-PHY Level 4 MegaCore Function November 2004, MegaCore Version 2.2.2 Errata Sheet Introduction This document addresses known errata and documentation changes for version v2.2.2 of the POS-PHY Level
More informationAltera JESD204B IP Core and ADI AD9680 Hardware Checkout Report
2015.05.11 Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report AN-710 Subscribe The Altera JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP). The JESD204B
More informationIntel Quartus Prime Software Download and Installation Quick Start Guide
Intel Quartus Prime Software Download and Installation Quick Start Guide Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus, and Stratix
More informationConfiguration via Protocol (CvP) Implementation in Altera FPGAs User Guide
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide Subscribe UG-01101 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Configuration via Protocol (CvP) Implementation
More informationDesign Guidelines for 100 Gbps - CFP2 Interface
2014.01.16 AN-684 Subscribe This document shows an example layout design that implements a 4 x 25/28 Gbps CFP2 module interface that meets the insertion and return loss mask requirements proposed in the
More informationRLDRAM II Controller MegaCore Function
RLDRAM II Controller MegaCore Function November 2006, MegaCore Version 1.0.0 Errata Sheet This document addresses known errata and documentation issues for the RLDRAM II Controller MegaCore function version
More informationAN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current
AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current January 2009 AN-547-10 Introduction To save power, the MAX II CPLD can be completely powered down into hibernation mode
More informationActive Serial Memory Interface
Active Serial Memory Interface October 2002, Version 1.0 Data Sheet Introduction Altera Cyclone TM devices can be configured in active serial configuration mode. This mode reads a configuration bitstream
More informationEmbedded Memory Blocks in Arria V Devices
Embedded Memory Blocks in Arria V Devices 2 AV-52002 Subscribe The embedded memory blocks in the devices are flexible and designed to provide an optimal amount of small- and large-sized memory arrays to
More informationUpgrading to UniPHY-based Controllers from ALTMEMPHY-based Controllers
Upgrading to UniPHY-based Controllers from ALTMEMPHY-based Controllers 14 emi_rm_012 Subscribe The following topics describe the process of upgrading to UniPHY from DDR2 or DDR3 SDRAM High-Performance
More informationSerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices
SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Stratix 10 ES Editions Subscribe Send Feedback Latest document
More informationT3 Framer MegaCore Function (T3FRM)
MegaCore Function August 2001; ver. 1.02 Data Sheet Features Achieving optimum performance in the Altera APEX TM 20K device architecture, the multi-featured MegaCore Function meets your innovative design
More informationNios II Embedded Design Suite 6.1 Release Notes
December 2006, Version 6.1 Release Notes This document lists the release notes for the Nios II Embedded Design Suite (EDS) version 6.1. Table of Contents: New Features & Enhancements...2 Device & Host
More informationH-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
H-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationImplementing the Top Five Control-Path Applications with Low-Cost, Low-Power CPLDs
Implementing the Top Five Control-Path Applications with Low-Cost, Low-Power CPLDs WP-01146-1.2 White Paper Since their introduction in the mid-1980s and across all end markets, CPLDs have been design
More information9. Functional Description Example Designs
November 2012 EMI_RM_007-1.3 9. Functional Description Example Designs EMI_RM_007-1.3 This chapter describes the example designs and the traffic generator. Two independent example designs are created during
More information7. External Memory Interfaces in Cyclone IV Devices
March 2016 CYIV-51007-2.6 7. External Memory Interaces in Cyclone IV Devices CYIV-51007-2.6 This chapter describes the memory interace pin support and the external memory interace eatures o Cyclone IV
More informationUsing the Serial FlashLoader with the Quartus II Software
Using the Serial FlashLoader with the Quartus II Software AN-370-3.2 Application Note Introduction Using the interface, the Altera Serial FlashLoader (SFL) is the first in-system programming solution for
More informationCyclone II FPGA Family
ES-030405-1.3 Errata Sheet Introduction This errata sheet provides updated information on Cyclone II devices. This document addresses known device issues and includes methods to work around the issues.
More informationThe Automotive-Grade Device Handbook
The Automotive-Grade Device Handbook Subscribe AUT5V1 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents Overview... 1-1 Altera Automotive-Grade Devices... 1-1 Altera Automotive Qualifications...
More informationInterlaken IP Core (2nd Generation) Design Example User Guide
Interlaken IP Core (2nd Generation) Design Example User Guide UG-20051 2017.09.19 Subscribe Send Feedback Contents Contents 1 Quick Start Guide... 3 1.1 Directory Structure... 4 1.2 Design Components...
More informationUsing MAX 3000A Devices as a Microcontroller I/O Expander
Using MAX 3000A Devices as a Microcontroller I/O Expander August 2003, Ver 1.0 Application Note 265 Introduction Advantages of Using MAX 3000A Devices Many microcontrollers and microprocessors limit I/O
More informationIntel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim
Intel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim AN-828 2017.10.02 Subscribe Send Feedback Contents Contents 1... 3 1.1 Conventions...3 1.2 Glossary...3 1.3 Introduction...3 1.4 Design...
More information2. Mentor Graphics ModelSim and QuestaSim Support
November 2012 QII53001-12.1.0 2. Mentor Graphics ModelSim and QuestaSim Support QII53001-12.1.0 This chapter provides specific guidelines for simulation of Quartus II designs with Mentor Graphics ModelSim-Altera,
More informationSimple Excalibur System
Excalibur Solutions Simple Excalibur System August 2002, ver. 1.0 Application Note 242 Introduction This application note describes a simple Excalibur system design that consists of software running on
More informationFPGA Design Security Solution Using MAX II Devices
White Paper FPGA Solution Using MAX II Devices Introduction SRAM-based FPGAs are volatile devices. They require external memory to store the configuration data that is sent to them at power up. It is possible
More informationError Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide
Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide 11 Innovation Drive San Jose, CA 95134 www.altera.com Software Version 8. Document Version: 2. Document Date: June 28
More informationDSP Builder. DSP Builder v6.1 Issues. Error When Directory Pathname is a Network UNC Path
March 2007, Version 6.1 Errata Sheet This document addresses known errata and documentation changes for DSP Builder version 6.1. Errata are functional defects or errors which may cause DSP Builder to deviate
More informationSONET/SDH Compiler. Introduction. SONET/SDH Compiler v2.3.0 Issues
January 2005, Compiler Version 2.3.0 Errata Sheet Introduction This document addresses known errata and documentation changes for version 2.3.0 of the SONET/SDH Compiler. Errata are design functional defects
More informationAltera ASMI Parallel II IP Core User Guide
Altera ASMI Parallel II IP Core User Guide UG-20068 2017.05.08 Last updated for Intel Quartus Prime Design Suite: 17.0 Subscribe Send Feedback Contents Contents 1... 3 1.1 Ports...4 1.2 Parameters... 5
More informationLegacy SDRAM Controller with Avalon Interface
Legacy SDRAM Controller with Avalon Interface January 2003, Version 1.0 Data Sheet Introduction PTF Assignments SDRAM is commonly used in cost-sensitive applications requiring large amounts of memory.
More informationUsing MAX II & MAX 3000A Devices as a Microcontroller I/O Expander
Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander March 2004, ver 2.0 Application Note 265 Introduction Advantages of Using MAX II & MAX 3000A Devices Many microcontroller and microprocessors
More informationIntel FPGA Temperature Sensor IP Core User Guide
Intel FPGA Temperature Sensor IP Core User Guide UG-01074 2017.09.14 Subscribe Send Feedback Contents Contents... 3 Intel FPGA Temperature Sensor Features...3 Intel FPGA Temperature Sensor Functional Description...
More informationConfiguration via Protocol (CvP) Implementation in Altera FPGAs User Guide
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com
More informationQuartus Prime Standard Edition Software and Device Support Release Notes Version 15.1
2015.11.02 Quartus Prime Standard Edition Software and Device Support Release Notes Version 15.1 RN-01080-15.1.0 Subscribe This document provides late-breaking information about the Altera Quartus Prime
More informationBoard Update Portal based on Nios II Processor with EPCQ (Arria 10 GX FPGA Development Kit)
Board Update Portal based on Nios II Processor with EPCQ (Arria 10 GX FPGA Development Kit) Date: 1 December 2016 Revision:1.0 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY,
More information