Low Power DRAM Evolution

Transcription

1 Low Power DRAM Evolution Osamu Nagashima Executive Professional Micron Memory Japan JEDEC Mobile & IOT Forum Copyright 2016 Micron Technology, Inc

2 How We Got Here Low Power DRAM evolved from a lowervoltage, lower-performance version of PC-DRAM designed for mobile packages to become one of the highest bandwidth-per-pin DRAMs available High resolution displays, high-resolution cameras, and 3D rendered content are the primary drivers for increased bandwidth in mobile devices

3 Mainstream DRAM Datarate by Type and Year of Introduction LPDDR PC-DDR

4 Evolution of Mainstream DRAM Energy Power Evolution DDR2 DDR3 DDR4 LPDDR2 LPDDR3 LPDDR4 ENERGY, PJ/BIT DATA RATE, MBPS

5 Typical Mobile Device Usage The percentage of active usage has greatly increased in recent years, driving an increase in memory bandwidth This has shifted limitations from standby battery life to active battery life and thermal limits 100% 80% 60% 40% 20% 0% 2% 8% 4% 4% 20% 20% 24% 22% 13% 12% 37% 34% Heavy user Light user Read Energy Write Energy Activate Energy Standby Energy Refresh Energy Self Refresh Energy

6 Near-Term Future This evolution of system limitations is driving future LPDRAM architectures, beginning with the evolution of the LPDDR4 standard Responding to the need for lower power, JEDEC is developing a reduced-i/o power version of LPDDR4, called LPDDR4X LPDDR4X will reduce the Vddq level from 1.1v to 0.6v Signaling swing will remain similar to LPDDR4 This allows the same receiver designs and specifications to be used for both LPDDR4 and LPDDR4X

7 LPDDR4X: I/O Energy Reduction Reducing Vddq from 1.1v to 0.6v produces about 40% I/O energy savings 4 LPDDR4 vs. LPDDR4X I/O Energy, Including Pre-Driver 3 I/O Energy, pj/bit 2 1 ~40% Decrease LP4, 60 Ohms LP4, 120 Ohms LP4, Unterm LP4X, 60 Ohms LP4X, 120 Ohms LP4X, Unterm Data Rate, Mbps

8 LPDDR4X I/O LPDDR4X reduces I/O channel energy to where it can sometimes be lower than predriver energy With LPDDR4X we ve reached the point where further reductions in Vddq have limited opportunity for energy savings The DRAM Rx limits the minimum signal swing Significant reductions in channel loading would be required to reduce pre-driver energy The DRAM core energy is now much larger than DRAM I/O energy

9 LPDDR4X: I/O Energy Breakdown Notice that at the most-efficient operating points (toward the right end of each line), the pre-driver energy is comparable to the channel energy Reducing Vddq below 0.6v will have limited impact, and may even increase total I/O energy 1.5 LPDDR4X I/O Energy, Channel+Termination vs. Pre-Driver I/O Energy, pj/bit Channel + Term, 60 Ohms Channel + Term, 120 Ohms Channel, Unterminated Pre-Driver, 60 Ohms Pre-Driver, 120 Ohms Pre-Driver, Unterminated Data Rate, Mbps

10 I/O vs. DRAM Core Energy LPDDR4X energy is dominated by the core Future energy reductions should focus on core efficiency in order to be significant 8 LPDDR4X Core Energy vs. I/O Energy Energy, pj/bit Core I/O, 48 Ohms I/O, 60 Ohms I/O, 120 Ohms I/O, Unterm Data Rate, Mbps

11 The Future All About Power Efficiency Power efficiency across a range of bandwidths is a more important attribute than peak bandwidth And cost is still very important JEDEC is beginning to consider LPDDR5 Data rates of 6.4Gbps or even higher are being considered Pushing DRAM performance to extreme speeds has consequences Higher I/O speeds than LPDDR4 will reduce power efficiency at all speeds

12 Effect of Increasing Speed Capability 6.4Gbps is approaching the limits of the DRAM process Pre-driver fanouts must be reduced As a consequence, deploying a DRAM I/O circuit capable of 6.4Gbps will cause an increase in pre-driver power at all speeds This will degrade the energy efficiency of the LP5 I/O compared to LPDDR4X at the lower-speeds - where it matters most! 3 LPDDR5 vs. LPDDR4X I/O Energy, Including Pre-Driver I/O Energy, pj/bit >50% 1600Mbps! LP5, 48 Ohms LP5, 60 Ohms LP5, Unterm LP4X, 48 Ohms LP4X, 60 Ohms LP4X, Unterm Data Rate, Mbps

13 Energy Cost for Higher Speeds Yes, DRAM can be made to function with very high data rates GDDR5 is a good example Adding GDDR5 to our power evolution chart, we see that energy/bit increases vs. LPDDR Power Evolution DDR3 LPDDR3 GDDR5 DDR4 LPDDR4 ENERGY, PJ/BIT DATA RATE, MBPS

14 Alternatives to LPDDR5 in Mobile Devices The challenge of LPDDR5 is to minimize I/O energy while supporting data rates of 6.4Gbps or higher Alternative solutions, include going wider More LPDDR4X I/O s could be a more power-efficient scheme Maintaining LPDDR4X data rates could enable wider PoP solutions that don t require significant changes in packaging There is discussion about using LPDDR3 I/O speeds, but this will: Require twice the I/O pins of LP4X for equivalent bandwidth, therefore increasing packaging costs and risks Unlikely to be more power efficient Another solution that could increase data per pin without a corresponding increase in pin count could be multi-level signaling This could be applied to both PoP and xmcp configurations

15 Attacking the Largest Component of DRAM Power The non-i/o portion of DRAM power now dominates DRAM manufacturers have already highly optimized designs to maximize power efficiency while meeting user requirements for highfrequencies and low latencies Significant reduction in the DRAM array voltage is not practical Lower voltage reduces the maximum charge that can be stored The resulting loss in performance and necessary increase in refresh rate would offset any power improvements

16 DRAM DVFS? Dynamic Voltage Frequency Scaling DVFS - has been used by many mobile components for years DVFS presents significant challenges for DRAM Building a DRAM that meets all of the demanding performance and reliability requirements at a wider voltage range is unlikely to improve efficiency Array core voltage must remain static Only peripheral circuits can operate at a wider range This means the array and periphery voltages must be separated

17 DRAM DVFS Additionally, verification and test of wide voltage ranges for peripheral circuits could be expensive This requirement is driven by the need in mobile applications to quickly change from low-frequency to higher-frequency operation while active Expecting the DRAM to continue operating at the lower frequency while voltage is ramped is required to avoid a stall The DRAM process does not scale to lower voltage well transistor performance decreases much faster than with today s logic processes Timing closure across an increased voltage range for DRAM is a very complex challenge

18 Two-Step DRAM DVFS More palatable to DRAM manufacturers could be a scheme that allowed for DRAM periphery operation at two discrete voltage levels, while leaving the array at one fixed level Much of the power savings can be realized Switching between these two discrete voltages must be fast enough that DRAM operation during the voltage ramp can be prohibited

19 Two-Step DRAM DVFS Low-to-high switching could be performed within the LPDDR4 tfc spec, therefore operation could be dis-allowed during the switch time This means DVFS can be automatically applied when the user switches operation between Frequency Set Points (FSP) Power efficiency can be improved by >30%

20 Future Challenges DRAM scaling challenges will add complexity to future memory systems twr will increase Native refresh times will shorten Especially if DRAM vendors reduce core voltage Error detection and correction will become a requirement ECC can reduce power and mitigate the performance impact of DRAM scaling challenges

21 Heterogenous Memory Space Mobile memory density continues to increase - do we really need maximum DRAM performance for the entire memory space? Would mobile systems be better served with a smaller, highspeed Local Main Memory and a larger, non-volatile memory array? A system like the one below could leverage emerging non-volatile memories that promise to be >1000x faster than NAND and much less costly than DRAM Storage Videos Music Apps OS

22 Logic-to-Logic Signaling DRAM I/O performance is nearing its limits Continuing to push I/O performance will decrease energy efficiency Addition of a logic die to the memory subsystem could enable higher-speed signaling, and therefore either higher performance or reduced SoC pincount A wide, slower interface to multiple DRAM and/or NVRAM die would be restricted to inside the memory package High-pincount packaging would not be required

23 Thank You