Dr. Yassine Hariri CMC Microsystems
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1 Dr. Yassine Hariri CMC Microsystems
2 Agenda MCES Workshop Agenda and Topics Canada s National Design Network and CMC Microsystems Processor Eras: Background and History Single core Multi-Many core Heterogeneous many core Heterogeneous compute platforms for R&D - a look out to Research topics Platform attributes in support of the research 2013, CMC Microsystems 2
3 Agenda MCES Workshop Agenda and Topics Processor Eras: Background and History Single core Multi-Many core Heterogeneous many core Heterogeneous compute platforms for R&D - a look out to Research topics Platform attributes in support of the research 2013, CMC Microsystems 3
4 MCES 13 Topics Applications and Algorithms Parallel applications for many-core platforms Communication and data movement Multiple sensors data fusion algorithms Architecture and Performance Analysis Design and mapping tools for heterogeneous mixed HW/SW parallel platforms Network on Chips : routing, arbitration and switch architecture Performance and power Analysis Programming models, Tools and Runtime Programming models and scalable software Energy efficient computation Adaptive runtime optimization OS/runtime support for heterogeneous processing cores, Compilers, profilers and debuggers Methodologies, flows, Metrics, and Benchmarking Reliability for safety critical applications 2013, CMC Microsystems 4
5 MCES Workshop Agenda (1/2) Session chair : Dr. Yassine Hariri, CMC Microsystems 2013, CMC Microsystems 5
6 MCES Workshop Agenda (2/2) Session chair : Dr. Gérard Berry, College-de-france 2013, CMC Microsystems 6
7 Agenda MCES Workshop Agenda and Topics Canada s National Design Network and CMC Microsystems Processor Eras: Background and History Single core Multi-Many core Heterogeneous many core Heterogeneous compute platforms for R&D - a look out to Research topics Platform attributes in support of the research 2013, CMC Microsystems 7
8 Agenda MCES Workshop Agenda and Topics Canada s National Design Network and CMC Microsystems Processor Eras: Background and History Single core Multi-Many core Heterogeneous many core Heterogeneous compute platforms for R&D - a look out to Research topics Platform attributes in support of the research 2013, CMC Microsystems 8
9 Multicores Further growth of established markets Multiprocessors are used everywhere Automotive Mobiles
10 35 YEARS OF MICROPROCESSOR TREND DATA Single Core Era 2 - Multi issue 1 - Scale Frequency 3 - SIMD Multi and Many-Core Era Original data collected and plotted by : M. Horowitz, F. Labonte, O. Shacham, K. Olukotun, L. Hammond and C. Batten Dotted line extrapolations by C. Moor 10
11 Three Eras of Processor Performance Single-Core Era Enabled by - Moore s Law - Voltage Scaling - Microarchitecture Constrained by X Power X Complexity Multi-Many Core Era Enabled by - Moore s Law - Desire for throughput - Desire for performance Constrained by X Power X Parallel SW availability X Scalability Heterogeneous Systems Era Enabled by - Moore s Law - Abundant data parallelism - Power efficient GPUs Constrained by X Power X Programming models X Communication overheads Source : The Salishan Conference on High Speed Computing, DATA PROCESSING IN EXASCALE-CLASS COMPUTER SYSTEMS Chuck Moore AMD Corporate Fellow & Technology Group CTO CMC Microsystems 11
12 Nature is massively parallel Parallel Heterogeneous Efficient Reliable 2013, CMC Microsystems 12
13 The heterogeneous computing vision Integration of different type of accelerators : Big CPUs, Little CPUs GPU FPGA 1000 s of RISC processors Examples: ARM : Big Little Xilinx : Zynq Qualcomm : Snap dragon Serious software challenge: How to make heterogeneous computing fabric easy to program? BIG CPU BIG CPU Little CPU FPGA GPU ANALOG 1000 s of RISCs Little CPU
14 Agenda MCES Workshop Agenda and Topics Canada s National Design Network and CMC Microsystems Processor Eras: Background and History Single core Multi-Many core Heterogeneous many core Heterogeneous compute platforms for R&D - a look out to 2020 Research topics Platform attributes in support of the research 2013, CMC Microsystems 14
15 Heterogeneous compute platforms for R&D Research Topics Development of parallel programming models and compilers targeting heterogeneous parallel systems Development of heterogeneous parallel architecture targeting specific application domains Development of parallel software IPs and applications targeting heterogeneous parallel systems (e.g. imaging, video, and next-generation immersive applications such as computational photography and augmented reality) Debug and trace of applications running on a heterogeneous parallel system CMC Microsystems 15
16 Agenda MCES Workshop Agenda and Topics Canada s National Design Network and CMC Microsystems Processor Eras: Background and History Single core Multi-Many core Heterogeneous many core Heterogeneous compute platforms for R&D - a look out to 2020 Research topics Platform attributes in support of the research 1.Heterogeneous parallel platform (HPP) 2.Synthesizable multi-core processors (HDL is given) 3.Embedded many-core SoC based platforms 4.Virtual prototyping environments 2013, CMC Microsystems 16
17 Heterogeneous parallel platform (HPP) Generic Specifications : Hardware CMC Microsystems 17
18 Heterogeneous parallel platform (HPP) Use scenario 1 : multiple users from same or different universities using the available accelerators independently CMC Microsystems 18
19 Agenda MCES Workshop Agenda and Topics Canada s National Design Network and CMC Microsystems Processor Eras: Background and History Single core Multi-Many core Heterogeneous many core Heterogeneous compute platforms for R&D - a look out to 2020 Research topics Platform attributes in support of the research 1.Heterogeneous parallel platform (HPP) 2.Synthesizable multi-core processors (HDL is given) OpenSparc T2 Heracle NoC FPGA-based Prototyping Environment 3.Embedded many-core SoC based platforms 4.Virtual prototyping environments 2013, CMC Microsystems 19
20 OpenSPARC CMC Microsystems 20
21 Heracles in Mesh Configuration M. Kinsy, Heracles: Fully synthesizable parameterizable mipsbased multicore system, Tech. Rep. MIT-CSAIL- TR , MIT, CMC Microsystems 21
22 Parallel platform Generic Specifications : Software Tools for developing highly optimized parallel software Reuse of legacy software Use standard parallel programming models or create new ones OS : heterogeneity and Real-time processing capability Power efficiency, Performance, Reliability for safety, flexibility, scalability, reconfigurability Tools for manycore Parallelizing tools System analysis Debug Applications Medical nursing Automotive Computer vision Programming models APIs Extended OS API Legacy API Application Specific API Manycore OS Real-time GP OS Special OS Heterogeneous parallel platform Consultation with researchers & community feedback Added value: Methodologies Reference designs Support Training Workshops CMC Microsystems 22
23 FPGA Prototyping Environment CMC Microsystems 23
24 FPGA Prototyping Platform NoC1 NoC 2 NoC3 NoC4 CMC Microsystems 24
25 Multi-FPGA Design Flow 2013, CMC Microsystems 25
26 Prototyping Design Flow Partition view What if analysis 2013, CMC Microsystems 26
27 FPGA Prototyping Platform Boot Sequence 2013, CMC Microsystems 27
28 Agenda MCES Workshop Agenda and Topics Canada s National Design Network and CMC Microsystems Processor Eras: Background and History Single core Multi-Many core Heterogeneous many core Heterogeneous compute platforms for R&D - a look out to 2020 Research topics Platform attributes in support of the research 1.Heterogeneous parallel platform (HPP) 2.Synthesizable multi-core processors (HDL is given) 3.Embedded many-core SoC based platforms 4.Virtual prototyping environments 2013, CMC Microsystems 28
29 STHORM Vision Accelerator STHORM is a many-core highly parallel programmable accelerator IP for Embedded parallel applications 28nm R&D test chip with 69 processors, 1 MB memory, 80 GFLOPs, < 1.5W peak power consumption, < 20 mm 2 OpenCL 1.1 programmable, SDK available CMC Microsystems 29
30 STHORM Eval. Board & Main Components Map 2013 CMC Microsystems 30
31 Agenda MCES Workshop Agenda and Topics Canada s National Design Network and CMC Microsystems Processor Eras: Background and History Single core Multi-Many core Heterogeneous many core Heterogeneous compute platforms for R&D - a look out to 2020 Research topics Platform attributes in support of the research 1.Heterogeneous parallel platform (HPP) 2.Synthesizable multi-core processors (HDL is given) 3.Embedded many-core SoC based platforms 4.Virtual prototyping environments Simics (Windriver) Virtualizer (Synopsys) Virtual System Platform (Cadence) 2013, CMC Microsystems 31
32 Symposium 2013 and ITAC 19th National Executive Forum Technologies for Digital Living: Trends Towards 2025 Heterogeneous Platform Planning for Embedded System R&D October 15, :30 p.m. Hilton Lac Leamy, Walker Room Join us to help specify the technology attributes of your research platforms. Meeting objective: Capture heterogeneous platform specifications for proc urements and preliminary work on new NDN proposals Agenda 1. Quick overview on the National Design Network and CMC support for research a nd startups 2. Embedded system research topics: discussion and feedback 3. Platform attributes in support of the research: discussion and feedback 2013, CMC Microsystems 32
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