Aim High. Intel Technical Update Teratec 07 Symposium. June 20, Stephen R. Wheat, Ph.D. Director, HPC Digital Enterprise Group

Transcription

1 Aim High Intel Technical Update Teratec 07 Symposium June 20, 2007 Stephen R. Wheat, Ph.D. Director, HPC Digital Enterprise Group

2 Risk Factors Today s s presentations contain forward-looking statements. All statements made that are not historical facts are subject to a number of risks and uncertainties, and actual results may differ materially. Please refer to our most recent Earnings Release and our most recent Form 10-Q Q or 10-K K filing available on our website for more information on the risk factors that could cause actual results to differ. Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, visit v Intel Performance Benchmark Limitations ( Rev. 7/19/06

3 Real World Problems Driving Petascale & Beyond 1 ZFlops 100 EFlops 10 EFlops 1 EFlops 1 EFlops 100 PFlops Real World Exascale Problem SUM Of Top500 #1 10 PFlops 1 PFlops 100 TFlops 10 TFlops 1 TFlops 100 GFlops 10 GFlops 1 GFlops Aerodynamic Example real Analysis: world challenges: 1 Petaflops Laser Full Optics: modeling of an aircraft in 10 all conditions Petaflops Molecular Green airplanes Dynamics in Biology: 20 Petaflops Aerodynamic Genetically Design: tailored medicine 1 Exaflops Computational Understand Cosmology: the origin of the universe 10 Exaflops Turbulence Synthetic in fuels Physics: everywhere 100 Exaflops Computational Accurate extreme Chemistry: weather prediction 1 Zettaflops Source: Dr. Steve Chen, The Growing HPC Momentum in China,, June 30 th, 2006, Dresden, 100 MFlops Germany What we can model today with <100TF

4 Silicon Future 90nm nm nm nm nm New Intel technology generation every 2 years Intel R&D technologies drive this pace well into the next decade 25 nm 22nm nm nm nm 2017 Roadmap Research

5 Intel Design & Process Cadence 2 YEARS Shrink/Derivative Xeon 5000 Intel Core Microarchitecture Xeon 5100 & nm Five Microprocessors in One Platform 2 YEARS Shrink/Derivative PENRYN New Microarchitecture NEHALEM 45nm 2 YEARS Shrink/Derivative WESTMERE New Microarchitecture GESHER 32nm 5 All dates, product descriptions, availability and plans are forecasts and subject to change without notice.

6 Flops Processor Performance 1.E+12 1.E+11 1.E+10 1.E+09 Intel Pentium 4 Architecture Intel Pentium III Architecture Intel Core Microarchitecture 1.E+08 Intel Pentium II Architecture Intel Pentium Architecture 1.E E Reaching Petascale with ~100,000 Processors in 2010* Assuming approx. 100Glops processors * Petascale assumes 10 s s of PF Peak Performance and 1PF Sustained Performance on HPC Applications. plications.

7 Why Multi-Core? Performance Power 1.00x Max Frequency Relative single-core frequency and Vcc

8 Over-clocking 1.73x Performance Power 1.13x 1.00x Over-clocked (+20%) Max Frequency Relative single-core frequency and Vcc

9 Under-clocking 1.73x Performance Power 1.13x 1.00x 0.87x 0.51x Over-clocked (+20%) Max Frequency Under-clocked (-20%) Relative single-core frequency and Vcc

10 Multi-Core Energy-Efficient Efficient Performance 1.73x Dual-Core Performance Power 1.73x 1.13x 1.00x 1.02x Over-clocked (+20%) Max Frequency Dual-core (-20%) Relative single-core frequency and Vcc

11 All Large Core Multi-threaded threaded Cores Mixed Large and Small Core All Small Core Goal: Energy Efficient Petascale with Multi-threaded threaded Cores Note: the above pictures don t t represent any current or future Intel products

12 Increasing Throughput through Parallelism Amdahl s s Law: Parallel Speedup = 1/(Serial% + (1-Serial%)/N*) 12 Cores 48 Cores 144 Cores Single Core Performance Relative Performance System Performance Assuming 100% parallel software Large Medium Small Large Medium Small * N = number of cores

13 Teraflops Research Chip 100 Million Transistors 80 Tiles 275mm 2 First tera-scale programmable silicon: Teraflops performance Tile design approach On-die mesh network Novel clocking Power-aware capability Supports 3D-memory Not designed for IA or product

14 What is Tera-scale? Teraflops of performance operating on Terabytes of data Entertainment TIPS Learning & Travel Performance GIPS MIPS 3D & Video Multi- Media RMS Multi-core Tera-scale Personal Media Creation and Management KIPS Text Single-core Health Kilobytes Megabytes Gigabytes Dataset Size Terabytes

15 Tera-scale Introduction Represents significant Intel transition from large cores to 32+ low-power, highly-threaded IA cores per die Motivations for a new architecture Enable emerging workloads and new use-models Low Power IA cores provide 4-5X 4 greater performance-power power efficiency Scaling beyond the limits of Instruction level parallelism and singles ingle-core power Tera-scale is NOT simply SMP-on on-die Will require complete platform and software enabling Parameter SMP Tera-scale Improvement Optimizations Bandwidth Latency 12 GB/s ~1.2 TB/s ~100X Massive bandwidth between cores 400 cycles 20 cycles ~20X Ultra-fast synchronization

16 Intel Tera-scale Research 100+ Research Projects Worldwide Microprocessor Examples: Scalable memory Multi-core architectures Specialized cores Scalable fabrics Energy efficient circuits Platform Examples: 3D Stacked Memory Cache Hierarchy Virtualization/Partitioning Scaleable OS s I/O & Networking Programming Examples: Speculative Multithreading Transactional memory Workload analysis Compilers & Libraries Tools ACCELERATE TRANSITION TO PARALLEL PROGRAMMING University Outreach Intel Press Intel Software College

17 Expected Tera-scale Insights Power management of many cores Research prototype enables extensive studies on fabric and core power consumption & management Physical implementation challenges of high speed fabric and multiple cores 3D stacked silicon technology On-chip bandwidth and latency impact

18 Tiled Design & Mesh Network Repeated Tile Method: Compute + router Modular, scalable Small design teams Short design cycle West neighbor To Future Stacked Memory North neighbor Compute Element Mesh Interconnect: Network-on-a-Chip South neighbor Cores networked in a grid allows for super high bandwidth communications in and between cores 5-port, 80GB/s* routers Low latency (1.25ns*) Future: connect IA/or and special purpose cores Router One tile East neighbor * When operating at a nominal speed of 4GHz

19 Fine Grain Power Management Novel, modular clocking scheme saves power over global clock New instructions to make any core sleep or wake as apps demand Chip Voltage & freq. control ( V, 0-5.8GHz) 0 Dynamic sleep STANDBY: Memory retains data 50% less power/tile FULL SLEEP: Memories fully off 80% less power/tile 21 sleep regions per tile (not all shown) Data Memory Sleeping: 57% less power Instruction Memory Sleeping: 56% less power Router Sleeping: 10% less power (stays on to pass traffic) FP Engine 1 Sleeping: 90% less power FP Engine 2 Sleeping: 90% less power Industry leading energy-efficiency efficiency of 16 Gigaflops/Watt

20 Research Data Summary Frequency Voltage Power 3.16 GHz 0.95 V 62W Bisection Bandwidth Performance 1.62 Terabits/s 1.01 Teraflops 5.1 GHz 1.2 V 175W 2.61 Terabits/s 1.63 Teraflops 5.7 GHz 1.35 V 265W 2.92 Terabits/s 1.81 Teraflops 1.01 Teraflops 62 Watts

21 More than the Cores Performance increase New instructions Cache improvements HW thread scheduling Baseline Number of cores Value of Tera-scale Research Just Adding Cores

22 Flops Processor Performance 1.E+12 1.E+11 1.E+10 1.E+09 Intel Pentium 4 Architecture Intel Pentium III Architecture Intel Core Microarchitecture 1.E+08 Intel Pentium II Architecture Intel Pentium Architecture 1.E E Reaching Petascale with ~100,000 Processors in 2010* Assuming approx. 100Glops processors * Petascale assumes 10 s s of PF Peak Performance and 1PF Sustained Performance on HPC Applications. plications.

23 Increasing Processor Performance 1.E+15 Peta 1.E+14 1.E+13 1.E+12 1.E+11 Tera Through Multi-threaded threaded Cores Flops 1.E+10 1.E+09 Giga 1.E+08 1.E E Pentium III Architecture 486 Pentium II Architecture Pentium Architecture Pentium 4 Architecture Intel Core uarch Reaching Petascale with ~5,000 Processors

24 Increasing I/O Signaling Rate to Fill the Gap 5,000 Frequency (Mhz) 4,000 3,000 2,000 1,000 Core GAP 0 Bus Silicon Photonics Source: Intel

25 Increasing Memory Bandwidth BW (GB/sec) Under 2W 3D Memory Higher BW within Power Envelope to Keep Pace Memory BW Constrained by Power 3D Memory Stacking Power and IO Signals Go Through DRAM to CPU Thin DRAM Die Through DRAM Vias Heat-Sink CPU DRAM Package Source: Intel

26 1 ZFlops 100 EFlops 10 EFlops 1 EFlops 100 PFlops 10 PFlops 1 PFlops 100 TFlops 10 TFlops 1 TFlops 100 GFlops 10 GFlops 1 GFlops What can we expect! HPC SUM Of Top500 #1 PC 100 MFlops Source: HPC - June 2006, Intel

27 Intel