Networks-on-Chip Router: Configuration and Implementation

Transcription

1 Networks-on-Chip : Configuration and Implementation Wen-Chung Tsai, Kuo-Chih Chu * 2 1 Department of Information and Communication Engineering, Chaoyang University of Technology, Taichung 413, Taiwan, ROC 2 Department of Electronic Engineering, Lunghwa University of Science and Technology, Taoyuan 333, Taiwan, ROC # azongtsai@cyut.edu.tw * kcchu@mail.lhu.edu.tw Abstract In this paper, we introduce a communication IP for System-on-Chip (SoC) namely Configurable Networks-on-Chip (CNoC-), which can perform various kinds of topology configuration for an on-chip network. With the flexible topology configuration and an adaptive routing scheme, CNoC- can enable a network with high performance using a relatively easy control. Synthesizable Register-Transfer-Level coding was designed and verified. Furthermore, a prototype based on Altera FPGA with a NIOS2 embedded micro-processor has been implemented to validate its practice. Keywords Field Programmable Gate Array; Networks on Chip; ; System on Chip 1. INTRODUCTION Embedded devices usually run just one or a few applications. Therefore, general-purpose processors are not suitable for running those applications because they are either too slow or too power hungry. Low-power embedded processors combined with hardware accelerators are the preferred choice for most designers. Recent designs for the embedded market use multi-core microprocessor to reduce power consumption. Future embedded systems may use a large number of heterogeneous cores to deliver the best trade-off between performance and power consumption. For these reasons, this paper presents a Configurable Networks-on-Chip (CNoC-) implemented by Altera FPGA (Field Programmable Gate Array) [1] and cooperating with a NIOS2 [2] embedded processor to demonstrate its function correctness and application extension for the many-core paradigm [3]. 2. BACKGROUND From on-chip interconnection networks [4] to the Networks-on-Chip (NoC) paradigm [5], packet switching is an aggressive, long-term approach for nano-scale interconnection networks [6]. To exchange messages among cores, the CNoC- was designed to transmit and receive packets through the physical interconnection channels between routers in the network. In contrast to the computer network, CNoC- covers functions of not only the data-link layer, but also the network layer to offload the processing overheads (e.g., packet routing procedures and switching controls) in embedded processors. In following sections, we will introduce the proposed techniques and demonstrate the enhanced network performance. Finally, a conclusion will be drawn. 3. ARCHITECTURE CNoC- is a 5 five port router as shown in Fig. 1. In which, Port 0 can be attached to a host entity (i.e., processor), Port1~Port4 are used to connect to neighbour routers [7]. Port 4 Port 0 Port1 Port3 Fig. 1 A five-port router Port 2 92

2 3.1. Applicably Topology By using CNoC-, various kinds of topologies can be configured, implementation examples are shown in Fig Switching Core The router switching core switches packets from input ports to output ports. The designed switching core includes Arbiter, Routing Table, Control Registers, s, Controllers, and Multiplexers as Fig 6 shows. Switch Switch Switch Switch Switch Switch Switch Switch Switch Arbiter Routing Table Control Register #8 Switch Switch Switch Switch Switch Switch #8 A 3x3 Mesh Switch A Tree with 7 s Fig. 2 Topology examples 3.2. Host and Neighbour- interfaces contain wrappers for each master and slave controller to transform Host and Neighbour- signals for the FIFO controls as shown in Fig. 3 and Fig. 4, respectively. Most kinds of processors can be attached to the CNoC- with little interface design modifications. In this paper, the Host interface is fitted to an Altera NIOS2 embedded processor [1]. Host Slave Master Controller TX FIFO Controller Switching Core ~~~~ RX Int. RX Int. RX Int. Path Sel. Path Sel. ~~~~ Path Sel. TX ~ ~~ ~ ~~~~ ~~~~ Fig. 5 Switching core Additionally, the Master/Salve interface of the switching core as Fig 7 shows. Switching Core RX Phy TX Phy SIPO Slave PISO RX Controller TX Controller CRC CRC Master s TX FIFOs Fig. 6 Master/Salve interface of switching core TX TX Fig. 3 Host interface of the router 4. SPECIFICATION Neighbour- Slave Master Controller Switching Core Fig. 4 Neighbour-router interface of the router Encapsulation and routing for packets are two essential functionalities of the designed router. Next, the proposed specifications are introduced as follows Packet Format Table 1 illustrates the packet format (32 bits/word), which can support up to (2 16 ) routers addressed in a network, and a packet data length from 0 to (0 ~ ) flits. Besides, the Destination Offset supports Direct Memory Access (DMA). The CRC (Cyclic Redundancy Check) field is or packet error detection. 93

3 TABLE 1 PACKET FORMAT Destination Address Control Code Source Address Data Length Destination Offset Extended Control Code Data ( flits) Fig. 8 displays the neighbour-router interface signals timing of the designed router. It is noticed that the interface supports a wait signal (RX_WAIT) and the RX_STA indicates the available FIFO space of the targeted router. CRC (1 flit) Moreover, in Tables 1 and 2, the Control Code field can enable an intelligent network system. For example, bits in the Control Code can be used to distinguish packet types (uni-cast, multicast, or broadcast), to record the packet sequence number (for packet retransmissions), to support Quality of Service (QoS), and so on. TABLE 2 CONTROL CODE FORMAT PT TC PC EC SN PT: Packet Type 000: Asynchronous Write Request Packet 001: Asynchronous Write Response Packet 010: Asynchronous Read Request Packet 011: Asynchronous Read Response Packet 100: Configuration Packet (CFG, means TC field is redefined) Others: Reserved TC: Type Code (of ASY [Asynchronous-Packet]) 00: ASY Free Route Others: Reserved TC: Type Code (of CFG) 00: CFG Write Request 01: CFG Write Response 10: CFG Read Request 11: CFG Read Response PC: Priority Code 000: Lowest priority ~~~~~~ 111: Highest priority EC: Error Control EC[0]: 0: Ack is required, 1: Ack is not required EC[1]: 0: Retry is permitted, 1: Retry is not permitted, SN: Sequence Number 4.2. Timing Diagram Fig. 7 illustrates the host (NIOS2) interface signals timing of the designed router. It is noticed that the interface design is referred to the specification of Altera NIOS2 [1]. Fig. 7 Host interface signals timing Fig. 8 Neighbour-router interface signals timing 4.3. Register Table 3 is the implemented router register table (32 bits/word). The registers can be programmed directly by the local host (i.e., the attached processor) or via a packet come from another remote router. TABLE 3 ROUTER REGISTER Name Address Description Add. 0x0000 Address Channel Num. 0x0000 Channel Number TABDA[3:0] 0x0001 Destination Add. 3~0 TABDA[7:4] 0x0002 Destination Add. 7~4 TABDA[b:8] 0x0003 Destination Add. b~8 THPRI[3:0] 0x0004 Threshold of Pri. 4~1 Reserved 0x0005 Reserved ~ 0xFFFE Testing 0xFFFF For Testing 4.4. Routing and Flow Control Scheme Each router owns a routing table (cf. TABDAx in Table 3), which keeps the priority of output ports to other routers (the table is predefined according to the network topology). In general, the router choices the first priority except the expected port is congested. This policy gives a router the ability to choice another path to avoid the heavy traffic region. Besides, the threshold (cf. THPRIx in Table 3) of congested levels to enable a re-route can be adjusted. As Fig. 9 shows, when a packet in and would like to go to, it will choice the path via instead of, because s FIFO have more free space than that free FIFO space in. 94

4 SW FIFO Status = 4 superior transit throughput due to less arbitration transmission overheads in routers. FIFO SIZE Effect SW FIFO Status = 1 X X SW FIFO Status SW FIFO Status Throughput (word) SIZE : 16 word SIZE : 1 word Fig. 9 Routing policy Traffic Variation (ns) 5. PERFORMANCE ANALYSES In this section, FIFO size, packet size, routing function, and FPGA performance of the implemented CNoC- are evaluated Analyses of FIFO and Packet Sizes Referring to Fig. 10, we adopted a star topology with five routers as the analysis configuration and compared the performance results with a native switching method. The FIFO size can be programmed via a QUE_LENTH parameter in the CNoC- Register- Transfer-Level (RTL) design, and the packet size can be adjusted in the Data_Length field of the proposed packet header (cf. Table 1) Fig. 10 Configuration of size effect analyses The first diagram in Fig. 11 shows that a larger FIFO size has higher traffic variations tolerances compared with a small size FIFO. According to the second diagram in Fig. 11, transmissions with bigger size packets (16 words per packet) achieve Xmit Data (packet/word) PACKET SIZE Effect Packet Size (word) Xmit Packets Xmit Words Fig. 11 Performance analyses of diverse FIFO sizes and packet sizes 5.2. Analyses of Adaptive Routing In Fig. 12, at issues packets to at. There are 3 paths to be selected. We list the paths from the shortest to the longest as follows: Path1 ( ), Path2 ( ), Path3 ( ). As the number above the shows, received 397 packets during 100 us simulation time, most of them are coming via the shortest path (Path1) Fig. 12 Configuration of adaptive routing analyses

5 Next, we enforced local traffic jams on Path1 ( to ) as shown in Fig. 13. We found that packets can be rerouted to other passable paths (i.e., Path2 and Path3) to avoid the hot traffic spots. The total packets received by are decreased slightly in the identical simulation time of 100 us. 201 (100) 88(232) 395(397) path can be greatly reduced in an Application Specific Integrated Circuit (ASIC) design. TABLE 3 FPGA PERFORMANCE Tool Quartus II Version 7.2 Device Stratix II, EP2S90F1020C5 Utilization 14 % Frequency MHz A NIOS2 embedded micro-processor [1] is attached to the designed router as Fig. 15 shows. The functional correctness of packet sending and receiving via a NIOS2 have been validated. 106(65) Fig. 13 Routing analyses with local traffic jams NIOS2 Packets In -> Packets Out < Port1 Last, we enforced local traffic jams on Path1 ( to ) and Path2 ( to ) as shown in Fig. 14. We found that packets can be rerouted to another passable path (i.e., Path3) to avoid the hot traffic spots. The total packets received by are decreased slightly in the identical simulation time of 100 us. Port4 Port 3 37 (201) 39(88) 317(106) 393(395) Fig. 14 Routing analyses with local traffic jams 5.3. FPGA Performance The CNoC- was designed in Register- Transfer-Level (RTL), verified with ModelSim [8], and implemented by Altera FPGA [1]. We list the FPGA performance indexes in Table 3. The maximum operation frequency is MHz, which is large than the FPGA board clock rate of 50 MHz. The delay of the design critical Port3 Fig. 15 CNoC router attaching with a NIOS2 To measure the performance of a switch, we adopted a network configuration as shown in Fig. 13. In which, issues a packet of length 15 to, the transmission path is. Besides, the cycle time is 10 ns. In Fig. 16, Point 1 shows that the received the same packet (4 header + 11 data) transmitted from. Point 2 indicates the total transmission latency is 560 ns. In Fig. 17, Point 3 reveals that transmission delay of a switch is 120 ns. Point 4 displays that the switch operation in a pipeline fashion, it can process one data unit in per cycle time. In the designed system, a data unit is 32-bit, and the maximal operation frequency is MHz. Accordingly, the bandwidth supported by the CNoC- could be up to 2.4 Gbps. 96

6 Fig. 16 Transmission integrity and latency Fig. 17 Transmission delay and pipelining 6. CONCLUSIONS In this paper, a Configurable Networks-onChip (CNoC-) was proposed to support an on-chip, packet-switching based network infrastructure for the coming many-core system-on-chip designs. CNoC- supported with packet routing and switching are functions corresponding to the network and data-link layers. We list the features of the designed CNoC- as follows: 97 Synthesisable HDL coding in Verilog Test-bench comprises a suit of host model and switch design Support packetized communication Support master & slave interface of host and device models Support adaptive routing scheme Support adaptive flow control

7 Evaluations on comprehensive traffic patterns showed that CNoC- can enhance network performance by well setting the router s configurable control register set. Besides, the designed packet format reserved many fields for further extensions. We believe that such a flexible architecture of CNoC- will support advanced applications and satisfy diverse communication requirements in the nextgeneration deep-submicron chip designs. ACKNOWLEDGMENT This work was supported by National Science Council, ROC, grants NSC E and MOST E REFERENCES [1] AlTERA Limited, NIOS2. i2-index.html [2] AlTERA Limited, FPGA2. [3] AlTERA Limited, From Multicore to Many-Core: Architectures and Lessons. [4] W.J. Dally and B. Towles, Route Packets, Not Wires: On-Chip Interconnection Networks, in Proc. of the 38th ACM/IEEE Design Automation Conference, pp , January [5] L. Benini and G. De Micheli, Networks on Chips: a New SoC Paradigm, IEEE Computer, Vol. 35, No. 1, pp , January [6] W.J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, [7] W.C. Tsai, Y.J. Shih, and B.S. Lyu, A Configurable Networks-on-Chip Using Altera FPGA and NIOS2 Embedded Processor, International Conference on Advanced Information Technologies, Taichung, Taiwan, April [8] Mentor Graph Limited, ModelSim. 98