A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on
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1 A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on on-chip Donghyun Kim, Kangmin Lee, Se-joong Lee and Hoi-Jun Yoo Semiconductor System Laboratory, Dept. of EECS, Korea Advanced Institute of Science and Technology (KAIST) International Symposium on Circuits and Systems 2005 Donghyun Kim 1
2 Outline Introduction Motivation Related Works Proposed Crossbar Switch Structure - Adaptive Bandwidth control scheme - Input/Output port Performance Evaluation - Traffic generators & MPEG 4 modeling Implementation Result Conclusion International Symposium on Circuits and Systems 2005 Donghyun Kim 2
3 Introduction System-on-Chip (SoC) design Lots of heterogeneous IPs Process scales down (Process variation) Higher clock frequency Providing efficient interconnection is difficult Reliable interconnection channel is required Smaller clock domain Network-on-Chip (NoC) provides solutions for SoC design Structured Interconnection GALS communication International Symposium on Circuits and Systems 2005 Donghyun Kim 3
4 Motivation Variations on bandwidth. <Homogeneous IPs> <Heterogeneous IPs > 1) CPU Mem CPU Mem CPU Mem Interconnection Channel CPU Mem CPU Mem CPU Mem Identical Processing Units Small Bandwidth Variation 1) Deepu Talla, et. al. Texas Instruments, Anatomy of a Portable Digital Mediaprocessor International Symposium on Circuits and Systems 2005 Donghyun Kim 4
5 Motivation (Cont d) Conventional crossbar switch is not efficient building block of the NoC. Performance is degraded due to insufficient bandwidth. Waste of power or silicon area. Input port 1 Input port 2... Input port N-1 Input port N... Output port 1 Output port Output port N-1... Output port N International Symposium on Circuits and Systems 2005 Donghyun Kim 5
6 Related Works No considerations for NoC traffic conditions. FLEXBAR NAMOO A 51mW 1.6GHz On- Chip Network [CICC 2002] [CICC 2003] [ISSCC 2004] Improved channel utilization Light-weight crossbar switch scheduler Partial activation Low power crossbar switch International Symposium on Circuits and Systems 2005 Donghyun Kim 6
7 Proposed Switch Structure Additional bus accelerates heavily loaded input port. Bandwidth is temporally doubled Normal Transfer International Symposium on Circuits and Systems 2005 Donghyun Kim 7
8 Bandwidth Control Scheme Additional bus enables adaptive bandwidth control. < Low Bandwidth > < High Bandwidth > FIFO has unused entry 4 Cycles / Packet FIFO full 2 Cycles / Packet International Symposium on Circuits and Systems 2005 Donghyun Kim 8
9 Input Port Buffer status determines use of additional bus. Request to Output port Input port Request to Additonal Bus Scheduler Grant Input Packet 22 Destination, Priority, Burst length Input Port Controller Additional Bus Grant Additional Bus Switch Fabric FIFO ( 88bit per packet) Bus Usage Info. (1bit line) International Symposium on Circuits and Systems 2005 Donghyun Kim 9
10 Output Port Order of physical transfer unit is aligned at the output port. International Symposium on Circuits and Systems 2005 Donghyun Kim 10
11 Simulation Setup Traffic generators Case 1 2 Num. of TG slow 6 4 Num. of TG fast TG slow 6 ~ TG fast (8 steps) TG slow 1X speed TG 1.14X 1.14X speed 3 Crossbar switches ~ TG 1.86X 1.86X speed TG fast 2X speed International Symposium on Circuits and Systems 2005 Donghyun Kim 11
12 Throughput Comparison Maximum 27% improvement Case 1 Case 2 Case 3 Case 4 International Symposium on Circuits and Systems 2005 Donghyun Kim 12
13 Latency Comparison Case 1 Case 2 Maximum 41% improvement Case 3 Case 4 International Symposium on Circuits and Systems 2005 Donghyun Kim 13
14 MPEG 4 Example MPEG 4 system is modeled on a mesh NoC. 1) E.B. Van der Tol. et. al. Mapping of MPEG-4 Decoding on a Flexible Architecture Platform International Symposium on Circuits and Systems 2005 Donghyun Kim 14
15 Implementation Result Synthesis result and power comparison Estimated Area (unit inverters) Maximum Operating Frequency Power Consumption (at 400MHz) Energy consumption Energy Consumption Conventional MHz 66.8 mw Conventional 0.99 mj / MB Proposed MHz 76.7 mw Proposed 0.92 mj / MB 7% improvement in energy consumption! International Symposium on Circuits and Systems 2005 Donghyun Kim 15
16 FPGA Implementation Proposed Crossbar switch is verified with various IPs. RISC CPU Proposed Crossbar Switch Graphic Processor International Symposium on Circuits and Systems 2005 Donghyun Kim 16
17 Conclusion A Crossbar switch with adaptive bandwidth control is designed and verified. Additional bus enables adaptive bandwidth control. Maximum 27% and 41% improvements in through-put and latency are achieved. With Adaptive bandwidth control scheme, efficient integration of heterogeneous IPs in NoC design is enabled. International Symposium on Circuits and Systems 2005 Donghyun Kim 17
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