OASIS Network-on-Chip Prototyping on FPGA
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1 Master thesis of the University of Aizu, Feb. 20, 2012 OASIS Network-on-Chip Prototyping on FPGA m , Kenichi Mori Supervised by Prof. Ben Abdallah Abderazek Adaptive Systems Laboratory, Master of Computer Science and Engineering in the Graduate School of the University of Aizu, Japan 2012/2/20 MT2011 1
2 Contents Background and Contribution System Architecture ONoC Router design Target Applications SPL Insertion Algorithm Evaluation Results Simulation Parameters Hardware Complexity Topology Optimization Performance Comparison Conclusion 2012/2/20 MT2011 2
3 Background: Network-on-Chip Network on Chip(NoC) provides a way of realizing interconnections on silicon and largely alleviate the limitations of bus-based solutions Processing elements are connected via a packet switched communication network P1 P2 P3 P1 P2 P3 s s s P4 P5 P6 P4 P5 P6 s s s P: Processing element S: Switch Bus-based system Network-on-Chip system 2012/2/20 MT2011 3
4 Background: OASIS Network-on-Chip OASIS 4x4 network architecture OASIS* NoC employs n x m mesh topology Network size can be changed rely on given applications Mesh topology congenitally has unfair communication * A. Ben Abdallah, M.Sowa, Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization, JASSST2006, Dec. 4-9th, /2/20 MT2011 4
5 Motivations Using traffic generators need to define many assumptions and approximations It is not enough to evaluate a NoC router s parameters (switching, scheduling, flow control, Buffer size and routing) effects and trade-offs Not accurate hardware and performance evaluation Mesh topology whose PEs are connected as uniform without consideration of the network load balance It degrades the overall performance significantly 2012/2/20 MT2011 5
6 Contributions Implementation of Optimized NoC (ONoC) on FPGA with Real Applications To evaluate accurate Power consumption, Area utilization and Performance Optimization for given applications with Short Pass Link(SPL) and evaluate accurate hardware complexity and performance 2012/2/20 MT2011 6
7 Contents Background and Contribution System Architecture ONoC Architecture Target Applications SPL Insertion Algorithm Evaluation Results Simulation Parameters Hardware Complexity Topology Optimization Performance Comparison Conclusion 2012/2/20 MT2011 7
8 ONoC Architecture (1/3) Optimized Network-on-Chip(ONoC) is designed based on OASIS NoC ONoC employs following functions Topology Mesh with SPL Routing XY routing Switching Wormhole-like Flow control Stall / go Scheduler Matrix arbiter SPL Topology example: 3x3 mesh with SPL ONoC employs mesh topology with Short Pass Link(SPL) To reduce latency which cause from a lot of hops XY routing is suitable for mesh topology 2012/2/20 MT2011 8
9 ONoC Architecture (2/3) ONoC employs following functions 1 st stage 2 nd stage 3 rd stage Topology Routing Switching Flow control Scheduler Mesh with SPL XY routing Wormhole-like Stall / go Matrix arbiter ONoC router has 3 pipeline stages Figure: ONoC router architecture 1 st stage: has input module which implements buffers module 2 nd stage: includes routing, flow control and Matrix arbiter 3 rd stage: includes Crossbar which forwards flits to neighbor routers 2012/2/20 MT2011 9
10 ONoC Architecture (3/3) Flow control mechanism Arbitration mechanism Matrix arbiter Avoiding buffer overflow method is stall/go When the priority i > j, P(i,j) becomes 1 and P(j, i) become 0 highest Merely state machine is used, and the module block to send packet in upstream router. (a) (b) highest 2012/2/20 MT
11 ONoC Router design RTL view Arbiter Router Input module Input data enter to these modules There are input ports for 5 directions Crossbar Input port and Arbiter output data enter here Arbiter and flow control It output data to Each input port request adequate direction output signal to arbiter and it send s grant signal to them Figure: RTL view output from Quartus II 2012/2/20 MT
12 Target Applications (1/2) Dimension reversal Hotspot Dimension reversal is a communication method based on transposed matrix Each node sends messages to a node with an address of the reversed dimension index Hotspot traffic has particular components receive traffic additionally to the random traffic (1,2) and (2,1) which assumed as receiving high frequently transmission 2012/2/20 MT
13 JPEG encoder Target Applications (2/2) RGB data loading, RGB to YUV conversion, Y, Cr, Cb calculations (derivation, quantization and Huffman encoding), synchronization, JPEG data stream checker and JPEG data storing Y, Cr, Cb calculations are executed in parallel Synchronization module synchronize these three data, so it needs to wait all calculations finish 2012/2/20 MT
14 SPL insertion process SPL insertion Algorithm Formulas The number of SPL decision for measuring communication frequency by calculating the whole communication volume and target communication volume Insert commu. selection Simulation and Insertion distance of communications is calculated by Manhattan distance. The source address is expressed by (ix, iy), and the destination address of j is expressed by (jx, jy). Total cost can calculate by multiply by above two calculations 2012/2/20 MT
15 Contents Background and Contribution System Architecture ONoC Architecture Target Applications SPL Insertion Algorithm Evaluation Results Simulation Parameters Hardware Complexity Topology Optimization Performance Comparison Conclusion 2012/2/20 MT
16 Design and Development Environment Design Tools Dimen. Hotspot JPEG Language: Verilog-HDL Software: Quartus II 11.0 Simulation tool: ModelSim- Altera 6.6 Device: Stratix III FPGA board Target applications Dimension Reversal Hotspot JPEG encoder partitioning Hardware compile RGB bitstream 24'b ; 24'b ; 24'b ; 24'b ; 24'b ; 24'b ; 24'b ; 24'b ; 24'b ; 24'b ; Network size info. Execution time Behavior Model RTL code Synthesis FPGA Hardware complexity NoC parameter Verilog- HDL Quartus II Stratix III 2012/2/20 MT
17 Dimension reversal & Hotspot parameters Parameter Original OASIS ONoC Topology 4x4 Mesh 4x4 Mesh with SPLs Budget 0 5% Flow control Stall/go Stall/go Switching wormhole like wormhole like Routing Algorithm XY routing XY routing Flit size 28bit 28bit Buffer depth 4 4 Input flits 1000/node 1000/node 2012/2/20 MT
18 Dimension reversal complexity OASIS Original ONoC-SPL1 ONoC-SPL2 ONoC-SPL3 Area (ALUTs) 9,008 / 113,600 ( 8 % ) 9,119 / 113,600 ( 8 % ) 9,272 / 113,600 ( 8 % ) 9,605 / 113,600 ( 8 % ) Speed MHz MHz MHz MHz Power Consumption Additional hardware Budget < 5% mw mw mw mw % 2.93% 6.63% 2012/2/20 MT
19 Hotspot complexity OASIS Original ONoC-SPL1 ONoC-SPL2 ONoC-SPL3 Area (ALUTs) 10,041 / 113,600 ( 9 % ) 10,130 / 113,600 ( 9 % ) 10,302 / 113,600 ( 9 % ) 10,911 / 113,600 ( 10 % ) Speed MHz MHz MHz MHz Power Consumption Additional hardware mw mw mw mw % 2.60% 8.66% Budget < 5% 2012/2/20 MT
20 Dimension reversal and Hotspot with SPL insertion Dimension reversal with SPL Hotspot with SPL Communication frequency (3,0) -> (0,3): (0,3) -> (3,0): Distance (3,0) -> (0,3): 6 (0,3) -> (3,0): 6 Communication 2 SPL insert to frequency Distance 2 SPL insert to -(3,0) -> (0,3) -(0,3) -> (3,0) (0,3) -> (1,0): (3,3) -> (1,1): (2,0) -> (2,3): (0,3) -> (1,0): 4 (3,3) -> (1,1): 4 -(0,3) -> (1,0) -(3,3) -> (1,1) 2012/2/20 MT
21 JEPG encoder parameters Parameter Original OASIS ONoC Topology Mesh Mesh with SPLs Budget 0 5% Flow control Stall/go Stall/go Switching wormhole like wormhole like Routing Algorithm XY routing XY routing Flit size 55bit 55bit Buffer depth 4 4 Input data size is 96x96, 27.2KB 2012/2/20 MT
22 JEPG encoder complexity OASIS ONoC-SPL1 ONoC-SPL2 ONoC-SPL3 Area (ALUTs) 28,401 / 113,600 ( 25 % ) 28,733 / 113,600 ( 25 % ) 29,138 / 113,600 ( 26 % ) 29,616 / 113,600 ( 26 % ) Speed MHz MHz MHz MHz Power Consumption Additional hardware Budget < 5% mw mw mw mw % 2.59% 4.28% 2012/2/20 MT
23 JPEG encoder with SPL RGB data Y: d_q_h Cr: d_q_h JPEG out S S 11 S 21 S RGB to RGB 0.09 Cb: d_q_h Synchro nization 0.09 Checker S 00 S S S 30 Communication frequency (0,0) -> (1,0): 0.27 (2,1) -> (2,0): 0.18 (0,0) -> (1,1): 0.09 Distance (0,0) -> (2,1): 3 (1,1) -> (2,0): 2 (0,0) -> (1,1): 2 3 SPL insert to (0,0) -> (2,1) (1,1) -> (2,0) (0,0) -> (1,1) 2012/2/20 MT
24 Throughput (flits/cycle) Throughput comparison ONoC-SPL throughput increase 32.3 % on average /2/20 MT
25 Execution time Performance comparison ONoC-SPL execution time decreased by 30.1 % on average Dimension Reversal (μs) Hotspot(μs) JPEG time (x10^1 ms) 5 0 OASIS ONoC-SPL1 ONoC-SPL2 ONoC-SPL3 2012/2/20 MT
26 Throughput (flits/cycle) JPEG encoder Latency and execution time Comparison Latency (μs) 43.4 % ONoC-SPL 3 reduce 43.4 % Latency, 43.7 % execution time 43.7 % OASIS ONoC-SPL1 ONoC-SPL2 ONoC-SPL3 2012/2/20 MT
27 Conclusion I implemented prototyped ONoC on FPGA, and evaluate performance and hardware complexity SPL insertion algorithm is proposed to reduce the latency I conclude ONoC with SPL, Dimension reversal slightly increased by 2.93% extra hardware, Hotspot increased by 2.60% and JPEG encoder increased by 4.28% The execution time in ONoC, Dimension reversal decreased by 29.7%, Hotspot decreased by 16.9% and JPEG encoder decreased by 43.7%, by SPL insertion and power consumption was slightly increased by 0.49% on average 2012/2/20 MT
28 Future work Research about fully adaptive routing that can increase the throughput and reduce total power consumption 2012/2/20 MT
29 Thank you for listening 2012/2/20 MT
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