Advanced Verification Topics. Bishnupriya Bhattacharya John Decker Gary Hall Nick Heaton Yaron Kashai Neyaz Khan Zeev Kirshenbaum Efrat Shneydor

Transcription

1 шт Bishnupriya Bhattacharya John Decker Gary Hall Nick Heaton Yaron Kashai Neyaz Khan Zeev Kirshenbaum Efrat Shneydor

2 Preface xv 1 Introduction to Metric-Driven Verification Introduction Failing to Plan = Planning to Fail Metric-Driven Verification Building Strong Testbench Foundations Simulation Isn't the Only Way Low Power isn't Just the Designer's Problem Reuse Isn't Just About Testbench Components Does Speed Matter? What About Scalability? Is Metric-Driven Verification Just for RTL Hardware? How Do I Get Up to Speed with All this New Stuff? Summary 14 2 UVM and Metric-Driven Verification for Mixed-Signal Why Metric-Driven Verification for Analog? Approach and Scope Planning for Analog Verification Including Analog Properties Verification Plan Structured for Reuse Constructing a UVM-MS Verification Environment Analog Verification Blocks Analog Configuration Interface Threshold Crossing Monitor Architecture of a Sample Testbench 25 iii

3 2.6 Collecting Coverage Direct and Computed Coverage Collection Deciding on Coverage Ranges Trading Off Speed and Visibility Generating Inputs Dealing with Configurations and Settings Generating and Driving Digital Control Checking Analog Functionality Comparing Two Values Triggering a Check on Control Changes Measuring Signal Timing Comparing a Value to a Threshold Checking Frequency Response Using Assertions Checking Input Conditions Verifying Local Invariants Limitations on Assertion Checking of Analog Properties Dealing with Different Modeling Styles Clocks, Resets and Power Controls Driving Clocks Resets Power-Up and Power-Down Sequences Analog Model Creation and Validation Integrating the Test Environment Connecting the Testbench Connecting to Electrical Nodes System-Level Parameters and Timing Supporting Several Model Styles In A Single Testbench Interfacing Between Real and Electrical Signals Creating Run Scripts and Other Support Files Recommended Directory Structure Closing the Loop Between Regressions and Plan Implementation of Coverage for Analog Updating the Verification Plan With Implementation Data Regression Runs for Analog IP Single Simulation Runs Regressions Running Multiple Test Cases Moving Up to the SoC Level Mix-and-Match SoC-Level Simulation Updating the SoC-Level Test Plan 70 iv

4 Integrating Into the SoC-Level Testbench UVM-MS Universal Verification Blocks Wire Verification Component Simple register UVC Analog to Digital Converter (ADC) UVC Digital to Analog Converter (DAC) UVC Level Crossing Monitor Ramp Generator and Monitor Summary 94 3 Low-Power Verification with the UVM Introduction What is Unique about Low-Power Verification Understanding the Scope of Low-Power Verification Low-Power Verification Methodology Understanding Low-Power Verification Understanding Low-Power Design and Verification Challenges How Low-Power Implementations Are Designed Today Challenges for Low-Power Verification Low-Power Optimization Low-Power Architectures Low-Power Resources Ill 3.3 Low-Power Verification Methodology Ill 3.4 Low-Power Discovery and Verification Planning Low-Power Discovery Verification Planning System-Level Planning Hierarchical Planning Domain-Level Verification Planning A Note on Verifying Low-Power Structures Recommendations for Designs with a Large Number of Power Modes Creating a Power-Aware UVM Environment Tasks for a Low-Power Verification Environment Solution: Low-Power UVC UVC Monitor LP Sequence Driver UVM-Based Power-Aware Verification Executing the Low-Power Verification Environment LP Design and Equivalency Checking Low-Power Structural and Functional Checks 129 v

5 3.6.3 Requirements for Selecting a Simulator and Emulator Advanced Debug and Visualizations Automated Assertions and Coverage Legal Power Modes and Transitions Automatic Checking of Power Control Sequences Verification Plan Generated from Power Intent Common Low-Power Issues Power-Control Issues Domain Interfaces System-Level Control Summary Multi-Language UVM Overview of UVM Multi-Language UVC Requirements Providing an Appropriate Configuration Exporting Collected Information to Higher Levels Providing Support for Driving Sequences from Other Languages Providing the Foundation for Debugging of All Components Optional Interfaces and Capabilities Fundamentals of Connecting e and SystemVerilog Type Conversion Function Calls Across Languages Passing Events Across Languages Configuring Messaging e Over Class-Based SystemVerilog Environment Architecture Configuration Generating and Injecting Stimuli Monitoring and Checking SystemVerilog Class-Based over e Simulation Flow in Mixed e and SystemVerilog Environments Contacting Cadence for Further Information UVM SystemC Methodology in Multi-Language Environments Introduction to UVM SystemC Using the Library Features for Modeling and Verification Connecting between Languages using TLM Ports Example of SC Reference Model used in SV Verification Environment Reusing SystemC Verification Components Summary 193 vi

6 5 Developing Acceleratable Universal Verification Components (UVCs) Introduction to UVM Acceleration UVC Architecture Standard UVC Architecture Active Agent Passive Agent Acceleratable UVCs UVM Acceleration Package Interfaces uvm_accel_pipe_proxy_base Task and Function Definitions (SystemVerilog) uvm_accel_pipe_proxy_base Task and Function Definitions (e) SCE-MI Hardware Interface SCE-MI Input Pipe Interface SCE-MI Output Pipe Interface Building Acceleratable UVCs in System Verilog Data Items Acceleratable Driver (SystemVerilog) Building Acceleratable UVCs in e Data Items Acceleratable Driver (e) Collector and Monitor Summary Summary 221 The Authors 223 Index 227 vii