Synchronized Progress in Interconnection Networks (SPIN) : A new theory for deadlock freedom
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1 ISCA 2018 Session 8B: Interconnection Networks Synchronized Progress in Interconnection Networks (SPIN) : A new theory for deadlock freedom Aniruddh Ramrakhyani Georgia Tech (aniruddh@gatech.edu) Tushar Krishna Georgia Tech (tushar@ece.gatech.edu) Paul V. Gratz Texas A&M University (pgratz@tamu.edu)
2 2 Network Routing J B A F G E C H K Deadlock D I
3 3 Routing Deadlocks A Routing Deadlock is a cyclic buffer dependency chain that renders forward progress impossible. Deadlock A F B E C D
4 4 Routing Deadlocks A Routing Deadlock is a cyclic buffer dependency chain that renders forward progress impossible. Deadlocks are a fundamental problem in both off-chip and onchip interconnection networks. Cause system breakdown and kill chips. Deadlocks are hard to detect during functional verification. Manifest after a long use time. Depend on : traffic pattern, injection rate, congestion. Show up due to system wear out faults and power-gating of network elements which are hard to simulate. Need a solution for functional correctness!!
5 5 Solution I: Dally s Theory Defines a strict order in acquisition of links and/or buffers which ensures a cyclic dependency is never created. Higher to Lower not allowed A F B E C D
6 6 Solution I: Dally s Theory Defines a strict order in acquisition of links and/or buffers which ensures a cyclic dependency is never created. Implementations: Turn model [5], XY routing, Up- Down routing [20]. Limitations: Routing Restrictions: Increased Latency, Throughput loss, Energy overhead Require large no. of VCs for fully adaptive routing.
7 7 Solution II: Duato s Theory Adds buffers to create a deadlock free escape path that can be used to avoid/recover from deadlocks. Implementation: turn restrictions in escape-vc. A F F VC0 Escape-VC B E C D E VC0 Escape-VC
8 8 Solution II: Duato s Theory Adds buffers to create a deadlock free escape path that can be used to avoid/recover from deadlocks. Implementation: turn restrictions in escape-vc. Limitations: Energy and Area overhead of escape VCs. Additional routing tables/logic for routing within escape-vc.
9 9 Other Solutions Solution III: Flow Control Restrict injection when no. of empty buffers fall below a threshold Implementation: Bubble Flow Control [9] Limitation: Implementation Complexity, Throughput Loss. Solution IV: Deflection Routing Assign every flit to some output port even if they get misrouted. Implementation: BLESS [10], CHIPPER [35] Limitation: Livelocks, non-minimal routing
10 10 Comparison of Deadlock Freedom Theories Theory Metric Acyclic CDG not Required No Packet Injection Restrictions Livelock Free VC cost for Mesh Routing Minimal Adaptive Topology Independent Dally 1 6 Duato Flow Control Deflection Routing SPIN 1 2 Can we do better??
11 11 Outline Routing Deadlocks State of the Art Dally s Theory Duato s Theory Flow Control Routing Deflection Routing SPIN : Synchronized Progress in Interconnection Networks Evaluations Conclusion
12 12 SPIN : Key Idea Simultaneous Synchronized Movement of all deadlocked packets in the loop is called a spin. A B C F E D What if: We coordinate the movement of every packet to the next hop at a given time?? Deadlock spin complete Simultaneous Synchronized Movement
13 13 SPIN : Key Idea Simultaneous Synchronized Movement of all deadlocked packets in the loop is called a spin. Each spin leads to one hop forward movement of all deadlocked packets. One spin may not resolve the deadlock. If so, spin can be repeated Deadlock is guaranteed to be resolved in a finite number of spins [proof in paper, Sec. III]
14 14 SPIN : Key Idea A B C F E D First spin complete Second spin complete
15 15 SPIN : Key Idea E D Deadlock Resolved F A C B Packets E &B exit the loop
16 16 Outline Routing Deadlocks State of the Art SPIN : Synchronized Progress in Interconnection Networks Key Idea Implementation Example Micro-architecture FAvORS Evaluations Conclusion
17 17 SPIN: Implementation Example SPIN is a generic deadlock freedom theory that can have multiple implementations. We choose a recovery approach as deadlocks are rare scenarios (See Sec. II-F). Our Implementation: Detect the Deadlock. Coordinate a time for spin. Execute the spin.
18 18 Implementation Example : Detect Deadlocks Use counters. Placed at every node at design time. Optimize by exploiting topology symmetry (See Static Bubble [6]). If packet does not leave in threshold time (configurable), it indicates a potential deadlock. Counter expired? deadlock. Send probe to verify
19 19 Implementation Example : Probe Msg. 1. Deadlock Detection 2. Coordinating the spin. 3. Executing the spin. A B F Probe E Probe Returns: Deadlock Confirmed Counter Expires at Node 5 Send Probe C D
20 20 Implementation Example : Probe Msg. Probe is a special message that tracks the buffer dependency. Probe returns to sender: Cyclic buffer dependence, hence deadlock. Next, send a move msg. to convey the spin time Upon receiving move msg., router sets its counter to count to spin cyle.
21 21 Implementation Example : Move Msg. 1. Deadlock Detection 2. Coordinating the spin. 3. Executing the spin. A B F Move E Set counter to count to spin cycle Move returns Send Move C D
22 22 Implementation Example : spin 1. Deadlock Detection A F 2. Coordinating the spin. 3. Executing the spin. B Counters expire together in the spin cycle E C D
23 23 Implementation Example : spin 1. Deadlock Detection 2. Coordinating the spin. 3. Executing the spin. F A E D B C
24 24 Multiple SPIN Optimization Resolving a deadlock may require multiple spins After spin, router can resume normal operation. Counter expires again, process repeated. Optimization: send probe_move after spin is complete. probe_move checks if deadlock still exists and if so, sets the time for the next spin. Details in paper (Sec. IV-B).
25 25 Outline Routing Deadlocks State of the Art SPIN : Synchronized Progress in Interconnection Networks Key Idea Implementation Example Micro-architecture FAvORS Evaluations Conclusion
26 26 Implementation Micro-architecture No additional links: Spl. Msgs. use the same links as regular flits. Spl. Msgs. have higher priority in link usage over regular flits. Links are anyways idle during deadlocks. Bufferless Forwarding: Spl. Msgs. are not buffered anywhere (either forwarded or dropped). Distributed Design: any router can initiate the recovery. 4% area overhead compared to traditional mesh router in 15nm Nangate [42].
27 27 Outline Routing Deadlocks State of the Art SPIN : Synchronized Progress in Interconnection Networks Key Idea Walkthrough Example Micro-architecture FAvORS Evaluations Conclusion
28 28 FAvORS Routing Algorithm SPIN is the first scheme that enables true one-vc fully adaptive deadlock-free routing for any topology. FAvORS : Fully Adaptive One-vc Routing with SPIN. Algorithm has two flavors: Minimal Adaptive Non-minimal Adaptive. Route Selection Metrics: Credit turn-around time Hop Count More details in paper (Sec. V).
29 29 Outline Routing Deadlocks State of the Art SPIN : Synchronized Progress in Interconnection Networks Evaluations Conclusion
30 30 Evaluations Network Configuration: Simulator gem5 simulator + Garnet 2.0 Network model Topologies 8x8 Mesh 1024 node Off-chip Dragon-fly Link Latency 1-cycle Inter-group: 3-cycle Intra-group: 1-cycle Traffic Synthetic + Multi-threaded (PARSEC) Synthetic
31 31 Evaluations : Baselines 8x8 Mesh: Design Routing Adaptivity Minimal Theory Deadlock Freedom Type West-first Routing Partial Yes Dally Avoidance Escape-VC Full Yes Duato Avoidance Static-Bubble [6] Full Yes Flow-Control Recovery 1024 Node Off-chip Dragon-fly: Design Routing Adaptivity Minimal Theory Deadlock Freedom Type UGAL [37] Full No Dally Avoidance
32 32 Saturation Throughput Latency (cycles) 1024-node Off-chip Dragon-fly: Bit-complement Inj. Rate (flits/node/cycle) Latency (cycles) Neighbor Inj. Rate (flits/node/cycle) UGAL_3VC SPIN UGAL_3VC Dally FAvORS_NMin_1VC SPIN Minimal_1VC SPIN 62% higher throughput compared to Minimal Routing 1-VC 50% higher throughput compared to UGAL_Dally 25% higher throughput compared to UGAL_Dally
33 33 Saturation Throughput 8x8 On-chip Mesh: Latency (cycles) Transpose (3-VC) Latency (cycles) % higher throughput Inj. Rate compared (flits/node/cycle) to West-first 3-VC West-First_3VC Static_Bubble_3VC Dally Flow-Control 10% higher throughput EscapeVC_3VC FAvORS_Min_3VC compared to Static-Bubble Duato SPIN 3-VC 8% higher throughput compared to Escape-VC 3-VC Transpose (1-VC) Inj. Rate (flits/node/cycle) West-First_1VC Dally FAvORS_Min_1VC SPIN 80% higher throughput compared to West-First 1-VC
34 34 Conclusion Deadlocks are a fundamental problem in Interconnection Networks. SPIN is a new deadlock freedom theory Simultaneous packet movement for deadlock recovery No routing restrictions or escape-vcs required. Enables true one-vc fully adaptive routing for any topology Salient Features of our Implementation: Scalable: Distributed Deadlock Resolution Plug-n-Play: topology agnostic 68% higher (Mesh) & 62% higher (dragon-fly) saturation throughput.
35 35 Conclusion Practical Applications: On-Chip Super-computers Datacenters Mesh (Intel Xeon Phi, Cavium Thunder X2) Dragon-fly (Cray XC Networks) JellyFish (HP), Fat Tree (Google) Irregular Topologies Faults (Static Bubble [6]) Power-gating (Router Parking[29]) NoC Generators Domain specific Accelerators FlexNoc (ARTERIS), Sonics GN (SONICS) Eyeriss [15] Thank you!!
36 Back-up 36
37 37 SPIN : Applications SPIN is a generic deadlock freedom theory Scalable: distributed deadlock resolution Plug-n-Play: doesn t require knowledge of topology SPIN can thus be used in : On-chip networks: Mesh (Intel SCC, Tilera Tile64) Supercomputers: Dragon-fly (Cray XC Networks) Datacenters: Jellyfish (HP), Fat Tree (Google) Static & Dynamically Changing Irregular topologies due to faults (Static Bubble [6]) & power-gating (Router Parking [29]) NoC Generators (Opensmart [13]) & Domain specific accelerator (Eyeriss[15])
38 38 Implementation Example : Probe Msg. A B F Probe E Probe Returns: Deadlock Confirmed Counter Expires at Node 5 C D Send Probe
39 39 Implementation Example : Move Msg. Cntr 1. Counter Expires 2. Send Probe 3. Send Move 4. Counter expires in spin cycle 5. Spin A B F Move E Set counter to count to spin cycle Move returns Send Move C D
store the deadlock path as we discuss later. The framework does not add any additional buffer/vc in the router datapath.
turn restrictions (for e.g., left turn is disallowed in Fig. 1(b)). Thus, packet F can move to the escape-vc of the downstream router and break the cyclic dependence. Flow control based schemes [8] restrict
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