Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers

Transcription

1 Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers Young Hoon Kang, Taek-Jun Kwon, and Jeff Draper {youngkan, tjkwon, University of Southern California / Information Sciences Institute Marina del Rey, CA/USA

2 Overview Introduction Dynamic packet fragmentation Fragmentation at credit stall Fragmentation at buffer empty stall Simulation results 20% latency reduction at the saturation point and 7.5% throughput improvement Place and Route 3% more cell area Power and Energy 15% less energy at the saturation point Conclusions 2

3 Introduction Packet-switched VC router Allocate and deallocate a VC per-packet basis Achieve high throughput with dynamic allocation of resources Lead to inefficient use of VCs at high traffic loads Propagate congestion of blocked-packet Regard VC buffer of blocked packet as fully occupied even when empty Credit stall Buffer empty stall 3

4 Introduction Packet-switched VC router Given limited number of VCs in NoCs, VC utilization is a key factor for performance improvement Prior work has characterized buffer utilization and proposed power optimization by placing idle buffers in a sleep mode Proposed router Dynamic packet fragmentation at blocking situations Exploit empty VC buffers Increase VC utilization and throughput Provide flexible flow control Reduce latency at high traffic 4

5 Fragmentation at credit stall Fragment at Credit stall Break VC allocation restriction by using idle buffers in other comparable VCs Regard credit stall as a congestion metric of downstream routers Give a chance to other VCs in the same input Route for a fragmented packet to a different path in adaptive routing scheme 5

6 Fragmentation at credit stall Fragment at Credit stall Router senses the lack of credits When the VC has 1 credit left and no more credits are returned VC controller fragments the packet to avoid credit stalls Convert the type field of the sending body to a virtual-tail flit Release the hold of output VC Attempt to acquire new VC Header flit copy serves as a virtual header flit 6

7 Fragmentation at buffer empty stall Fragment at buffer empty stall Prevent the mid-packet blocking from propagating to multiple routers Give other packets a chance to use the empty buffer 7

8 Fragmentation at buffer empty stall Fragment at buffer empty stall Router detects that it may encounter a buffer empty stall When the VC has a single flit in the input buffer and no flit coming into this buffer VC controller fragments the packet to avoid buffer empty stall Convert the type field of the sending body to a virtual-tail flit Release the hold of output VC Attempt to acquire new VC Header flit copy serves as a virtual header flit 8

9 Simulation results Design evaluation parameters Topology Mesh 4x4 Routing Dimension-order (XY) # of ports 5 # of VCs 4 Buffer per port 24 (6-entry depth per VC) Flit size 128 bits Packet length 8, 16 flits Latency (cycles) Base (8-flit) Base (16-flit) Fragment (8-flit) Fragment (16-flit) 0% 10% 20% 30% 40% 50% 60% Injection rate () Latency reduction 20% less latency at baseline saturation point of 52% injection rate Throughput improvement 7.5% more throughput Increased resource utilization and dynamic reaction capability more than compensate for the added overhead 9

10 Simulation results Fragmentation rate 200% 160% 120% 80% 40% 0% Fragment (8-flit) Fragment (16-flit) 0% 10% 20% 30% 40% 50% 60% Injection rate Latency (cycles) Size of the fragmented packet is determined by the number of buffer entries 8-flit packet is fragmented once 16-flit packet is fragmented up to twice Dynamic fragmentation shows 10% latency reduction at the saturation points of the statically fragmented packet % Fragment (8-flit) static 200% Fragment (16-flit) static Fragment (8-flit) Fragment (16-flit) 0% 10% 20% 30% 40% 50% 60% Injection rate 10

11 Place and Route Baseline Fragment Cell area µm² µm² Flit buffer 72% 60% Head buffer 0% 10% Crossbar 5.4% 5.5% VC ctrl 12% 14.1% Die size [820x820] µm² Density 76.32% 76.73% Critical path Technology Operating conditions 3.0 ns including wire delay IBM 90nm 1.0V, 25 C Overall cell area difference is approximately 3% Both routers are synthesized with clock gating to minimize dynamic power Baseline Fragment 11

12 Power & Energy Power consumption Every annotated switching activity is reflected in the power calculation using Synopsys Power Compiler Energy consumption Almost same energy at low injection rates 15% less energy near the saturation point 12

13 Conclusions On-chip router with dynamic packet fragmentation Increase VC utilization and relieve congestion Performance Up to 20% latency reduction 7.5% throughput improvement Future work Explore how the decision to fragment can be made more intelligently Assemble fragmented packets at intermediate routers 13