CSE 502 Graduate Computer Architecture. Lec 7-10 App B: Memory Hierarchy Review

Transcription

1 CSE 502 Graduate Computer Architecture Lec 7-10 App B: Memory Hierarchy Review Larry Wittie Computer Science, StonyBrook University and ~lw Slides adapted from David Patterson, UC-Berkeley cs252-s06 2/14,16,21,23/2012 1

2 Review from Last Lecture Conclusions for Control and Pipelining Quantify and summarize performance Ratios to VAX, Geometric Mean, Multiplicative Standard Deviation F&P: Benchmarks age, disks fail, single-point failure Control via State Machines and Microprogramming Pipelines just overlap tasks - easy for independent tasks Speed Up Pipeline Depth; if ideal CPI is 1, then: Pipeline depth Speedup = 1 + Pipeline stall CPI Cycle Cycle Time Time unpipelined pipelined Hazards limit performance on computers by stalling: Structural: need more HW resources Data (RAR, RAW,WAR,WAW): need forwarding, compiler scheduling Control: delayed branch or branch (taken/not-taken) prediction Exceptions and interrupts add complexity 2/14,16,21,23/2012 2

3 Outline Review Memory hierarchy Locality Cache design Virtual address spaces Page table layout TLB design options Conclusion 2/14,16,21,23/2012 3

4 Memory Hierarchy Review 2/14,16,21,23/2012 4

5 Since 1980, CPU has outpaced DRAM... Performance (1/latency) Q. How do architects address this gap? A. Put smaller, faster cache memories between CPU and DRAM. Create a memory hierarchy. CPU CPU 60% per yr 2X in 1.5 yrs Latency gap grew 50% per year DRAM 9% per yr DRAM 2X in 10 yrs Year 2/14,16,21,23/2012 5

6 Levels of the Memory Hierarchy Capacity Access Time Cost CPU Registers 100s Bytes <10s ns Cache K Bytes ns cents/bit Main Memory M Bytes 200ns- 500ns $ cents /bit Disk G Bytes, 10 ms (10,000,000 ns) cents/bit Tape Almost infinite sec-min cents/bit Registers Instr. Operands Cache Blocks Memory Pages Disk Files Tape Staging Xfer Unit prog./compiler 1-8 bytes cache cntl bytes OS 512-4K bytes user/operator Mbytes Upper Level faster Larger Lower Level 2/14,16,21,23/2012 6

7 Memory Hierarchy: Apple imac G5 (2004-5) Managed by compiler Managed by hardware Managed by OS, hardware, application yr Reg L1 Inst L1 Data L2 DRAM Disk Size in Bytes 1K 64K 32K 512K 256M 80G Latency in Cycles, Time 1 cyc, 0.6 ns 3 cyc, 1.9 ns 3 cyc, 1.9 ns 11 cyc, 6.9 ns 88 cyc, 55 ns 10 7 cyc, 12 ms Goal: Illusion of large, fast, cheap memory Let programs address a memory space that scales to the disk size, at a speed that is usually nearly as fast as register access imac G5 1.6 GHz 1600 (mem: 7.3) x Apple II imac G5 1.6 GHz clock, 55 ns DRAM vs Apple II 1 MHz, 400ns DRAM Perform: CPU 1600 X, DRAM 7.3 X faster in 27 yrs => 2X/ 2.5y, 9.3y 2/14,16,21,23/2012 7

8 imac s PowerPC 970 (G5): All caches on-chip L1 (64K Instruction) 1/2 KB R eg ist er s 512K L2 1/2 KB L1 (32K Data) Original = 64-bit single-core 2/14,16,21,23/2012 8

9 Cache Terminology to Understand 1 address trace Sequence of memory (block) addresses in the order accessed by running code 2 average memory access time (AMAT) The average time in cycles to satisfy a memory reference including any delays because of cache misses 3 block Group of successive memory words that fit in the data section of a cache entry 4 locality Near repetition of program memory accesses either in address value or in time 5-8 cache instruction cache data cache unified cache 9-11 direct mapped fully associative n-way set associative 12 set memory address tag field index field block offset block address write-back write-through write buffer write stall valid bit dirty bit write allocate 25 no-write allocate cache hit cache miss hit time miss rate 30 miss penalty memory stall cycles least recently used (LRU) random replacement memory references per instruction misses per instruction 36 virtual memory page page fault! 2/14,16,21,23/2012 9

10 The Principle of Locality The Principle of Locality: Program access a relatively small portion of the address space at any instant of time. Two Different Types of Locality: Temporal Locality (Locality in Time): If an item is referenced, it will tend to be referenced again soon (e.g., loops, reuse) Spatial Locality (Locality in Space): If an item is referenced, items whose addresses are close by tend to be referenced soon (e.g., straightline code, array access) For last 20 years, HW has relied on locality for speed by using fast cache copies of memory parts to lower average memory access time (AMAT) for programs Locality is a property of programs which is exploited in machine design. 2/14,16,21,23/

11 Programs with locality cache well... Memory Address (one dot per access) Space Time Bad locality behavior Spatial Locality Donald J. Hatfield, Jeanette Gerald: Program Restructuring for Virtual Memory. IBM Systems Journal 10(3): (1971) Temporal Locality 2/14,16,21,23/ Time=>

12 Memory Hierarchy: Terminology Hit: data appears in some block in the upper level (example: Block X) Hit Rate: the fraction of memory accesses found in the upper level Hit Time: Time to access the upper level which consists of RAM access time + Time to determine hit/miss Miss: data needs to be retrieved from a block in the lower level (Block Y) Miss Rate = 1 - (Hit Rate) Miss Penalty: Time to replace a block in the upper level + Time to deliver the block to the upper level Hit Time << Miss Penalty(=500 instructions on 21264!) To Processor From Processor Upper Level Memory Blk X Lower Level Large Size Memory Blk Y 2/14,16,21,23/

13 Cache Measures Hit rate: fraction, near 100%, found in that level So high that usually talk about Miss rate = 1 - Hit rate Miss rate fallacy: as MIPS to CPU performance, miss rate to average memory access time in memory Average memory-access time = Hit time + Miss rate x Miss penalty (ns or clocks) Miss penalty: time to supply a missed block from lower level, including any CPU-visible delays to save replaced write-back data to make room in upper level cache. { All active caches are full } {replacement time: time to make upper-level room for new block} access time: time to lower level = f(latency to lower level) transfer time: time to transfer block =f(bw between upper & lower levels) 2/14,16,21,23/

14 Four Questions for Memory Hierarchy (relative to both caches and DRAM for virtual memory) Q1: Where can a block be placed in the upper level? (Block placement) Q2: How is a block found if it is in the upper level? (Block identification) Q3: Which block should be replaced on a miss? (Block replacement) Q4: What happens on a write? (Write strategy) 2/14,16,21,23/

15 Q1: Where can a block be placed in the upper level? Memory block 12 placed in each 8-block cache: 3 cache organizations are shown below: Fully associative, direct mapped, 2-way set associative (S.A.) S.A. Mapping = Block Number Modulo (Number of Sets) (Cache blocks allowed to hold block 12, shown in blue.) Direct Mapped 2-Way Set Assoc Full Associative (12 mod 8) = 4 (12 mod 4=8/2) = Cache Memory /14,16,21,23/

16 Memory Address Fields to Find a Word in Cache Figure B.3 The three portions of an address in a set associative or direct-mapped cache. The tag is used to check all the blocks in the set, and the index is used to select the set. The block offset is the address of the desired data within the block. Fully associative caches have no index field. 2/14,16,21,23/ , Elsevier Inc. 16

17 Q2: How tell if block is in upper level cache? Bits = 18b: tag 8b index: 256 entries/cache ( 4b: 16 wds/block 2b: 4 Byte/wd) IMPORTANT SLIDE! or ( 6b: 64 Bytes/block 6 offset bits) Bits: (1-way) Direct Mapped Cache 16KB = 2 8=index sets x 1 blk/set x 2 6=4+2=offset B/blk Index => cache set Location of all possible blocks Must check tag for each block: No need to check index, offset bits Increasing associativity: Shrinks index & expands tag size Hit V Tag 18 bits Tag = Address (showing bit positions) Index Byte offset Data 512 bits Mux Block (a.k.a. Page) Address Tag Index 32 Data Capacity: 16KB = 256 x 1 x 64 Bytes 32 Block offset Bit Fields in Memory Address Used to Access Cache Word Virtual Memory Cache Block 256 entries Offset Bits of Bytes in Page 2/14,16,21,23/ Data

18 Data Cache Organization - Opteron Microprocessor Figure B.5 The 64 KB cache is twoway set associative with 64-byte blocks. The 9-bit index selects among 512 sets. The four steps of a read hit, shown as circled numbers in order of occurrence, label this organization. Three bits of the block offset join the index to supply the RAM address to select the proper 8 bytes. Thus, the cache holds two groups of bit words, with each group containing half of the 512 sets. Although not exercised in this example, the line from lower-level memory to the cache is used on a miss to load the cache. The size of address leaving the processor is 40 bits because it is a physical address and not a virtual address. Figure B.24 on page B-47 explains how the Opteron maps from virtual to physical for a cache access. 2/14,16,21,23/ , Elsevier Inc. 18

19 Miss Rates Versus Cache (Data) Capacity Figure B.9 Total miss rate (top) and distribution of miss rate (bottom) for each size cache according to the three C s for the data in Figure B.8. The top diagram shows the actual data cache miss rates, while the bottom diagram shows the percentage in each category. (Space allows the graphs to show one extra cache size than can fit in Figure B.8.) 2/14,16,21,23/ , Elsevier Inc. 19

20 Optimum Block Sizes in Small Caches Figure B.10 Miss rate versus block size for five different-sized caches. Note that miss rate actually goes up if the block size is too large relative to the cache size. Each line represents a cache of different size. SPEC2000 traces would take too long if block size were included, so these data are based on SPEC92 on a DECstation 5000 [Gee et al. 1993]. 2/14,16,21,23/ , Elsevier Inc. 20

21 Miss Rates vs Cache Size for Multilevel Caches Figure B.14 Second-level caches smaller than the sum of the two 64 KB first-level caches make little sense, as reflected in the high miss rates. After 256 KB the single cache is within 10% of the global miss rates. The miss rate of a single-level cache versus size is plotted against the local miss rate and global miss rate of a secondlevel cache using a 32 KB first-level cache. The L2 caches (unified) were two-way set associative with [random] replacement. Each had split L1 instruction and data caches that were 64 KB two-way set associative with LRU replacement. The block size for both L1 and L2 caches was 64 bytes. 2/14,16,21,23/ , Elsevier Inc. 21

22 Relative Execution Time by Level-2 Cache Size Figure B.15 The two bars are for different clock cycle delays for an L2 cache hit. The reference execution time of 1.00 is for an 8192 KB second-level cache with a 1-clock-cycle latency on a second-level hit. 2/14,16,21,23/ , Elsevier Inc. 22

23 Q3: Which block to replace after a miss? (After start up, cache is nearly always full) Easy if Direct Mapped (only 1 block 1 way per set index ) If Set Associative or Fully Associative, must pick a block: Random ( Ran ) Easy to implement, but not best. If only 2-way: 1bit/way LRU (Least Recently Used) LRU is best, but hard to implement if > 8-way Other LRU approximations better than Random Miss Rates for 3 Cache Sizes & Associativities Associativity 2-way 4-way 8-way DataSize LRU Ran LRU Ran LRU Ran 16 KB 5.2% 5.7% 4.7% 5.3% 4.4% 5.0% 64 KB 1.9% 2.0% 1.5% 1.7% 1.4% 1.5% 256 KB 1.15% 1.17% 1.13% 1.13% 1.12% 1.12% Random picks in big caches => ~ same low miss rate as LRU 2/14,16,21,23/

24 Q4: Write policy: What happens if write (store) data? Write-Through Write-Back Policy Data word written to cache block is also written to next lower-level memory Example, instr. sw to L1$ also goes to L2$ Write new data word only to 1 cache block Update lower level just before a written block leaves cache, so not lose true value Debugging Easier Harder Can read misses force writes? No Yes (no longer slow any reads; use write-buffer) Do repeated writes touch lower level? Yes, memory busier No Additional option -- let writes to an un-cached address allocate a new cache line ( write-allocate ), else just Write-Through. 2/14,16,21,23/

25 Write Buffers for Write-Through Caches Processor Cache Write Buffer Lower Level Memory Write buffer holds (addresses&) data awaiting write-through to lower levels Q. Why a write buffer? Q. Why a buffer, why not just one register? Q. Are Read After Write (RAW) hazards an issue for write buffer? A. So CPU not stall for writes A. Multi-write bursts are common before write-thru. A. Yes! Drain buffer before next read or check buffer addresses before read-miss. 2/14,16,21,23/

26 5 Basic Cache Optimizations Reducing Miss Rate 1. Larger Block size (reduce Compulsory, cold, misses) 2. Larger Cache size (reduce Capacity misses) 3. Higher Associativity (reduce Conflict misses) ( and multiprocessors have cache Coherence misses) (4 Cs) Reducing Miss Penalty 4. Multilevel Caches {total miss rate = (local miss rate k ), where means product of all items k, for k = 1 to max. } Reducing Hit Time (minimize cache latency) 5. Giving Reads Priority over Writes, since CPU is waiting. Read completes before earlier writes in write buffer 2/14,16,21,23/

27 Outline Review Memory hierarchy Locality Cache design Virtual address spaces Page table layout TLB design options Conclusion 2/14,16,21,23/

28 The Limits of Physical Addressing Programs used physical addresses of memory locations A0-A31 CPU D0-D31 Simple addressing method of archaic pre-1978 computers Data A0-A31 Memory D0-D31 All programs shared one address space: the physical address space Machine language programs had to be aware of the machine organization and load into memory areas not used by OS No way to prevent a program from accessing any machine resource in memory 2/14,16,21,23/

29 Solution Post-1978: Add Layer of Indirection Virtual Addresses Physical Addresses A0-A31 Virtual Physical A0-A31 CPU D0-D31 Address Translation Main Memory D0-D31 Data All user programs run in an standardized virtual address space starting at zero. Needs fast(!) Address Translation hardware, managed by the operating system (OS), to map each virtual address to physical memory Hardware supports modern OS features: Memory protection, Address translation, Sharing 2/14,16,21,23/

30 Three Advantages of Virtual Memory Translation: Program can be given consistent view of memory, even though physical memory is scrambled (pages of programs in any order in physical RAM) Makes multithreading reasonable (now used a lot!). Only the most important part of each program ( the working set ) must be in physical memory at any one time. Contiguous structures (like stacks) use only as much physical memory as necessary, yet still can grow later as needed, without recopying. Protection (most important now): Different threads (or processes) protected from each other. Different pages can be given special behavior; examples: (Read Only, Invisible to User Programs, Not Cached). Kernel and OS data are protected from access by user programs. Very important for protection from malicious programs. Sharing: Can map same physical page to multiple users. ( Shared memory holding C++ compiler for many users at once.) 2/14,16,21,23/

31 Same Size VM Pages Fit in Any Order in RAM Figure B.19 The logical program in its contiguous virtual address space is shown on the left. It consists of four pages, A, B, C, and D. The actual location of three of the blocks is in physical main memory and the other is located on the disk. 2/14,16,21,23/ , Elsevier Inc.

32 virtual address Page tables encode mappings of code s virtual addresses to physical memory address space Page Table page page page page OS manages the page table of each Virt. Add. Space ID Physical Memory Space frame frame frame frame A virtual address space (V.A.S.) is divided into blocks of memory called pages A machine usually supports pages of a few sizes (MIPS R4000) A page table is indexed by a virtual address Each valid page table entry codes the present physical memory frame address for its page 2/14,16,21,23/

33 virtual address Page Table page page page page Details of Page Table Physical Memory Space frame frame frame frame Page Table Ptr In Base Reg Virtual Address (for 4,096 Bytes/page) 12 V page no. offset index into page table Page Table 0 V Access Rights Page table maps virtual page numbers to physical frames ( PTE = Page Table Entry) Virtual memory treats main memory cache for disk PA table located in physical memory (V is valid bit) (Byte offset same in VA & PA) Ph page no. offset 12 Physical Address 2/14,16,21,23/

34 All page tables may not fit in memory! A table for 4KB pages for a 32-bit physical address space (max size 4GB) has 1M entries (4K 1M = 4G) Each process needs its own address space tables! Two-level Page Tables 32 bit virtual address P1 index P2 index Page Offset Single top-level table wired (stays) in main memory Only a subset of the 1024 second-level tables are in main memory; rest are on disk or unallocated 2/14,16,21,23/

35 Mapping Opteron-64 Virtual Address to Physical Address Figure B.27 The mapping of an Opteron virtual address. The Opteron virtual memory implementation with four page table levels supports an effective physical address size of 40 bits. Each page table has 512 entries, so each level field is 9 bits wide. The AMD64 architecture document allows the virtual address size to grow from the current 48 bits to 64 bits, and the physical address size to grow from the current 40 bits to 52 bits. How many bytes in each memory page? 2/14,16,21,23/ , Elsevier Inc. 35

36 Opteron TLB: Control Bits + Tag + Physical Page Number Figure B.24 Operation of the Opteron data TLB during address translation. The four steps of a TLB hit are shown as circled numbers. This TLB has 40 entries. The protection and access fields of each Opteron page table entry include: V-Valid, R/W-Read.Only/Read.Write, U/S-User.Access.OK/Supervisors.Only, D-Dirty (modified page in DRAM), A-Accessed.Recently (since A bit last zeroed), {bits not shown} Present.In.Memory/On.Disk.Only, Page.Size (4KB/4MB Page), No.Execute (Data.Only.Not.Code), Write.Thru/Back.Data.Caching, No.Caching 2/14,16,21,23/ , Elsevier Inc. 36

37 VM and Disk: Page replacement policy Set of all pages in Memory 2. Head pointer: Place page on free list if used ( accessed ) bit is still clear (=0). Schedule freed pages with dirty bit set to be written to disk. Dirty bit: page written. Used bit: set to 1 on any reference 1. Tail pointer: Clears (=0) used bits" in page table, saying page may not be recently used. Architect s role: support setting dirty and used bits dirty used Page Table... Freelist Free Pages 2/14,16,21,23/

38 TLB Design Concepts 2/14,16,21,23/

39 MIPS Address Translation: How does it work? Virtual Addresses Physical Addresses A0-A31 CPU D0-D31 Virtual Physical TLB also contains protection bits for virtual address A0-A31 Translation Look-Aside Memory Buffer D0-D31 (TLB) Data What is the Per-Process Translation Look-Aside Buffer (TLB) table of mappings A small very fast fully-associative cache of mappings from virtual to physical addresses Fast common case: If virtual address is in TLB, process has permission to read/write it. 2/14,16,21,23/ that it caches? Recently used VA PA entries.

40 TLB caches page table entries. The TLB Caches Page Table Entries virtual address page offset Page Table for current AddrSpaceID V Physical and virtual pages must be the same size! Here, 1024 Bytes/page each. Physical frame address TLB PAdd frame Vadd page physical address frame offset MIPS handles TLB misses in software (random replacement). Other machines use hardware. V=0 pages reside on disk or have not yet been allocated to this ASID. OS handles V=0 as a Page fault 2/14,16,21,23/

41 A Memory Access From Virtual Address to L2 Cache Hit Figure B.17 The overall picture of a hypothetical memory hierarchy going from virtual address to L2 cache access. The page size is 16 KB. The TLB is two-way (2-way) set associative with 256 (2*2 7 ) entries. The L1 cache is a direct-mapped 16 KB (2 8 *2 6 Byte), and the L2 cache is 4-way set associative with a total of 4 MB (4*2 14 *2 6 B). Both use 64-byte (2 6 ) blocks. The virtual address is 64 bits and the physical address is 40 bits. 2/14,16,21,23/ , Elsevier Inc. 41

42 Can TLB translation overlap cache indexing? {Maybe if cache is tiny.} Virtual Page Number Page Offset Tag Part of Physical Addr = Physical Page Number Index Byte Select Virtual Translation Look-Aside Buffer (TLB) Physical Cache Tags Valid Cache Data Cache Block Cache Tag = Cache Block Having cache index in page offset works, but Q. What is the downside? A. Inflexibility. Size of cache limited by page size. Hit Data out 2/14,16,21,23/

43 Problems With Overlapped TLB Access Overlapped access only works so long as the address bits used to index into the cache do not change as the result of VA translation This usually limits overlapping to small caches, large page sizes, or high n-way set associative caches if a large capacity cache is needed Example: suppose everything the same except that the cache is increased to 8 KBytes instead of 4 KB: 11 2 cache index virt page # disp 00 Solutions: go to 8KByte page sizes; go to 2-way set associative cache; or SW guarantee VA[13]=PA[13] This bit is changed by VA translation, but it is needed for cache lookup K 2-way set assoc cache 2/14,16,21,23/

44 Can CPU use virtual addresses for cache? Virtual Addresses Physical Addresses A0-A31 CPU D0-D31 Virtual Cache D0-D31 Virtual Physical Translation Look-Aside Buffer (TLB) A0-A31 Main Memory D0-D31 If cache index in virtual address, only cache misses use TLB! Downside: a subtle, fatal problem. What is it? (Aliasing) A. Synonym problem. If two address spaces share a physical frame, data may be in cache twice. Maintaining consistency is a nightmare. 2/14,16,21,23/

45 Aside for HW1: Head to Head ILP Comparison Processor Micro architecture Fetch / Issue / Execute Funct. Units Clock Rate (GHz) Transistors Die size Power Intel Pentium 4 Extreme Prescott Speculative dynamically scheduled; deeply pipelined; SMT (2004) 3/3/4 7 int. 1 FP M 122 mm W AMD Athlon 64 FX-55 / -57 Opteron Speculative dynamically scheduled (2004 / 05) 3/3/4 6 int. 3 FP 2.6 / M/114M 193/115 mm W/ 104 W IBM Power5 (1 core only) Speculative dynamically scheduled; SMT; 2 cores/chip (2004) 8/4/8 6 int. 2 FP M 300 mm 2 (est.) 80W (est.) Intel Itanium 2 Madison Statically scheduled VLIW-style (2004) 6/5/11 9 int. 2 FP M 423 mm W Sources: /14,16,21,23/

46 Summary #1/3: The Cache Design Space Several interacting dimensions cache size block size associativity replacement policy write-through vs write-back write allocation The optimal choice is a compromise depends on access characteristics» workload» use (I-cache, D-cache, TLB) depends on technology / cost Simplicity often wins Bad Good Cache Size Factor A Less Associativity Block Size Factor B More 2/14,16,21,23/

47 Summary #2/3: Caches The Principle of Locality: Program access a relatively small portion of the address space at any instant of time.» Temporal Locality: Locality in Time» Spatial Locality: Locality in Space Three Major Uniprocessor Categories of Cache Misses: Compulsory Misses: sad facts of life. Example: cold start misses. Capacity Misses: increase cache size Conflict Misses: increase cache size and/or associativity. Nightmare Scenario: ping pong effect! Coherence Misses (in multiprocessors): Avoid frequent use of shared variables in parallel programs. Write Policy: Write Through vs. Write Back Today CPU time is a function of (ops, cache misses) vs. just f(ops): Increasing performance affects Compilers, Data structures, and Algorithms 2/14,16,21,23/

48 Summary #3/3: TLB, Virtual Memory Page tables map virtual address to physical address TLBs are important for fast translation TLB misses are significant in processor performance This decade is a funny time, since most systems cannot access all of 2nd level cache without TLB misses! The answer in newer processors is 2-levels of TLB. Caches, TLBs, Virtual Memory all understood by examining how they deal with four questions: 1) Where can a block be placed? 2) How is a block found? 3) What block is replaced on a miss? 4) How are writes handled? Today VM allows many processes to share single memory without having to swap all processes to disk; today VM protection is more important than memory hierarchy benefits, but computers are still insecure Short in-class open-book quiz on appendices A-C & Chapter 1 near start of next (2/28) class. Bring a calculator. Read Chapter 2 next. (Please put your best address on your quiz.) 2/14,16,21,23/

49 Unused Slides, Spring /14,16,21,23/

50 1977: DRAM faster than microprocessors Apple (1977) Latencies CPU clock: 1000 ns DRAM access: 400 ns Steve Jobs Steve Wozniak 2/14,16,21,23/