Phastlane: A Rapid Transit Optical Routing Network
|
|
|
- Calvin Cooper
- 5 years ago
- Views:
Transcription
1 Phastlane: A Rapid Transit Optical Routing Network Mark Cianchetti, Joseph Kerekes, and David Albonesi Computer Systems Laboratory Cornell University
2 The Interconnect Bottleneck Future processors: tens to hundreds of cores Dire need for fast and power efficient on-chip interconnect Nanophotonics Ultra-fast signal propagation High bandwidth density Low power O/E Translation Electrical Input Data V input - E/O Translation Photonic System Components Optical Coupler
3 Limitations of Nanophotonics Lack of fundamental building blocks Logic gates Memory structures Single routing layer Power loss of waveguide crossings Traditional Approach To Exploiting Photonics Source Node Direct Bus Path Upon formation, unimpeded data blasted from source to destination Destination Node
4 Respecting the Limitations Electrical Network Mesh Column Optical Network Dest Node Cornell Ring Architecture Columbia Architecture Corona Architecture FireFly Architecture Previous proposals largely bus-based Direct photonic links between source and destination Data blasted in a single optical transmission
5 Overview of Previous Work Feature Cornell Ring Corona Columbia Phastlane Network Topology Ring-bus Snake XBAR Torus Mesh Network Operation Snoopy Bus Fully Connected XBAR Electrical Setup Packet Switched Shared Resources None Destination Bus Router Channels Router Channels Shared Resource Arb. WDM Token Per Hop Per Hop Unit of Data Transfer Cache Line Cache Line >> Cache Line Cache Line
6 Phastlane Contributions Novel nanophotonic router architecture Hybrid optical/electrical packet-switched, mesh network Nanophotonics: High-speed, multi-hop packet transfers Electrical: Logic and buffering to handle packet conflicts
7 Phastlane Architecture Routing Arbitration Transmit: Node 0 to Node 10 Minimally impede flow of light from source to destination Simplified routing, arbitration Dual die configuration
8 Optical Node Operation Crossbar Resonators Optical Router
9 Electrical Node Operation Blocked packets are buffered locally Per port buffers, single processor buffer Output multiplexers connect to output port optical transmitters Electrical Node
10 Simplified Packet Routing XY Dimension-Order Per Hop Packet Control Hop Number Direction Encoding R Local R Straight R Straight R Left Straight R2 R Straight Source Routing Data/Address/Other Packets are dimension-order, source routed Portion of packet holds pre-computed routing bits Per hop control bits enable near-instant switch traversal
11 Per Hop Control Bits Hop Number R6 R5 R4 R3 R2 R1 Direction Encoding Local Straight Straight Straight Left Straight R 4 R 3 Frequency shift Empty Control Waveguide Router R1 examines control bits Per hop control groups set switch resonators Left, right, straight, local, broadcast Frequency translation Enables hop oblivious routing Left Right Straight Local Broadcast
12 Per Hop Control Bits Continued C1 C0 C0 C1 Control waveguide split into C0 and C1 WDM limitations Frequency and physical translation Enables hop oblivious routing
13 Competing Packets: Resolution N W E Packet Received S Two packets collide Collision resolution Packet collisions avoided by packet blocking Collision resolution performed on the fly
14 Drop Node N C1o C0o D2o D1o D00 D0 i D1 i D2i C0i C1i C1o C1o C1 o C0o C0o C0 o D2o D2o D2 o D1o D1o D1 o D00 D00 E D0 0 D0i D1i D2i C0i C1i C1 o C0o D2o D1o D00 D0i D1i D2i C0i C1i D0i D1i D2i C0i C1i C1 o C0o D2o D1o D00 D0i D1i D2i C0i C1i D0 i D1 i D2 i C0 i C1 i C1 o C0o D2o D1o D00 D0i D1i D2i C0i C1i C1i C0i D2i D1i D0i D00 D1o D2o C0o C1o D0i D1i C0i D0i D1i C0i N C1o C0o D2o D1o D00 D0 i D1 i D2i C0i C1i C1o C1 o C1 o C0o C0 o C0 o D2o D2 o D2 o D1 o D1 o E High-Speed Drop Network D0 i D1 i C0i C1i N N D0 i D1 C1o C0o D2o D1o D00 D2i C1o C0o D2o D1o D00 i D2i C0i C1i W D0 0 D0 0 D0 i D1 i D2 i C0 i C1 i C1 o C0o D2o D1o D00 D0i D1i D2i C0i C1i D0 i D1 i D2 i C0 i C1 i C1 o C0o D2o D1o D00 D0i D1i D2i C0i C1i D0i D1i C0i D0i D1i C0i E W E E W C1i D2i D00 D1o D2o C0o C1o N C1o C0o D2o D1o D00 D0 i D1 i D2i C0i C1i C1i D2i D00 D1o D2o C0o C1o N C1o C0o D2o D1o D00 D0 i D1 i D2i C0i C1i W D1o D00 D0i D1i D2i C0i C1i C1 o C0o D2o D1o D00 D0i D1i D2i C0i C1i C1i C0i D2i D1i D0i D00 D1o D2o C0o C1o C1o C0o D00 D0i C0i C1i C1 o C0 o D0 0 D0 i C0 i C1 i C1o C0o D0o D0i C0i C1i E W W C1i C0i D0i D0 0 C0o C1o C1i D2i D00 D1o D2o C0o C1o C1i D2i D00 D1o D2o C0o C1o Source Drop path gradually formed as packet passes through network Packet dropped if downstream buffer full Drop signal travels opposite data packet
15 Router Design Space Exploration
16 Evaluation Methodology Baseline Configuration XBAR 64 node, 8x8 mesh network topology Low latency, high bandwidth electrical network baseline Multi-port receive for destination packets Packet size: 80 bytes, single flit Synthetic and Splash benchmarks Baseline Node
17 Synthetic Benchmark Results Bit Comp Bit Rev Latency X Latency X Offered Traffic Offered Traffic Shuffle Transpose Latency X Offered Traffic Latency X Offered Traffic
18 Splash Performance Analysis 2X speedup across all benchmarks Electrical Optical Optical 64 Entry Buffers Optical Inf Buffers Network Speedup 0 Barnes Cholesky FFT Lu Ocean Radix Raytrace WaterNSq Waterspatial FMM
19 Splash Power Analysis 80% reduction in power across all benchmarks Electrical Optical Optical 64 Entry Buffers Relative Power Barnes Cholesky FFT Lu Ocean Radix Raytrace WaterNSq Waterspatial FMM
20 Conclusions Novel nanophotonic router architecture Packet-switched, hybrid optical/electrical mesh network Up to 8X performance improvement for synthetic workloads Up to 4X performance improvement, 80% power reduction, for Splash Future work Lower power broadcast scheme Improved allocation and flow control
Brief Background in Fiber Optics
The Future of Photonics in Upcoming Processors ECE 4750 Fall 08 Brief Background in Fiber Optics Light can travel down an optical fiber if it is completely confined Determined by Snells Law Various modes
EECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 14: Photonic Interconnect
1 EECS 598: Integrating Emerging Technologies with Computer Architecture Lecture 14: Photonic Interconnect Instructor: Ron Dreslinski Winter 2016 1 1 Announcements 2 Remaining lecture schedule 3/15: Photonics
Network-on-Chip Architecture
Multiple Processor Systems(CMPE-655) Network-on-Chip Architecture Performance aspect and Firefly network architecture By Siva Shankar Chandrasekaran and SreeGowri Shankar Agenda (Enhancing performance)
Lecture 22: Router Design
Lecture 22: Router Design Papers: Power-Driven Design of Router Microarchitectures in On-Chip Networks, MICRO 03, Princeton A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip
SIGNET: NETWORK-ON-CHIP FILTERING FOR COARSE VECTOR DIRECTORIES. Natalie Enright Jerger University of Toronto
SIGNET: NETWORK-ON-CHIP FILTERING FOR COARSE VECTOR DIRECTORIES University of Toronto Interaction of Coherence and Network 2 Cache coherence protocol drives network-on-chip traffic Scalable coherence protocols
EECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 12: On-Chip Interconnects
1 EECS 598: Integrating Emerging Technologies with Computer Architecture Lecture 12: On-Chip Interconnects Instructor: Ron Dreslinski Winter 216 1 1 Announcements Upcoming lecture schedule Today: On-chip
Index 283. F Fault model, 121 FDMA. See Frequency-division multipleaccess
Index A Active buffer window (ABW), 34 35, 37, 39, 40 Adaptive data compression, 151 172 Adaptive routing, 26, 100, 114, 116 119, 121 123, 126 128, 135 137, 139, 144, 146, 158 Adaptive voltage scaling,
826 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 6, JUNE 2014
826 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 6, JUNE 2014 LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip Cheng Li, Student Member,
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
Department of Computer Science and Engineering, Texas A&M University Technical eport #2010-3-1 seudo-circuit: Accelerating Communication for On-Chip Interconnection Networks Minseon Ahn, Eun Jung Kim Department
Lecture 15: NoC Innovations. Today: power and performance innovations for NoCs
Lecture 15: NoC Innovations Today: power and performance innovations for NoCs 1 Network Power Power-Driven Design of Router Microarchitectures in On-Chip Networks, MICRO 03, Princeton Energy for a flit
Shared Memory Multiprocessors. Symmetric Shared Memory Architecture (SMP) Cache Coherence. Cache Coherence Mechanism. Interconnection Network
Shared Memory Multis Processor Processor Processor i Processor n Symmetric Shared Memory Architecture (SMP) cache cache cache cache Interconnection Network Main Memory I/O System Cache Coherence Cache
Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers
Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers Young Hoon Kang, Taek-Jun Kwon, and Jeff Draper {youngkan, tjkwon, draper}@isi.edu University of Southern California
Interconnection Networks: Topology. Prof. Natalie Enright Jerger
Interconnection Networks: Topology Prof. Natalie Enright Jerger Topology Overview Definition: determines arrangement of channels and nodes in network Analogous to road map Often first step in network design
Lecture 18: Communication Models and Architectures: Interconnection Networks
Design & Co-design of Embedded Systems Lecture 18: Communication Models and Architectures: Interconnection Networks Sharif University of Technology Computer Engineering g Dept. Winter-Spring 2008 Mehdi
IITD OPTICAL STACK : LAYERED ARCHITECTURE FOR PHOTONIC INTERCONNECTS
SRISHTI PHOTONICS RESEARCH GROUP INDIAN INSTITUTE OF TECHNOLOGY, DELHI 1 IITD OPTICAL STACK : LAYERED ARCHITECTURE FOR PHOTONIC INTERCONNECTS Authors: Janib ul Bashir and Smruti R. Sarangi Indian Institute
Swizzle Switch: A Self-Arbitrating High-Radix Crossbar for NoC Systems
1 Swizzle Switch: A Self-Arbitrating High-Radix Crossbar for NoC Systems Ronald Dreslinski, Korey Sewell, Thomas Manville, Sudhir Satpathy, Nathaniel Pinckney, Geoff Blake, Michael Cieslak, Reetuparna
Lecture 13: Interconnection Networks. Topics: lots of background, recent innovations for power and performance
Lecture 13: Interconnection Networks Topics: lots of background, recent innovations for power and performance 1 Interconnection Networks Recall: fully connected network, arrays/rings, meshes/tori, trees,
Lecture 26: Interconnects. James C. Hoe Department of ECE Carnegie Mellon University
18 447 Lecture 26: Interconnects James C. Hoe Department of ECE Carnegie Mellon University 18 447 S18 L26 S1, James C. Hoe, CMU/ECE/CALCM, 2018 Housekeeping Your goal today get an overview of parallel
Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance
IEEE/ACM 45th Annual International Symposium on Microarchitecture Dynamic Reconfiguration of D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance Randy Morris, Avinash Karanth
Lecture: Interconnection Networks
Lecture: Interconnection Networks Topics: Router microarchitecture, topologies Final exam next Tuesday: same rules as the first midterm 1 Packets/Flits A message is broken into multiple packets (each packet
A Multilayer Nanophotonic Interconnection Network for On-Chip Many-core Communications
A Multilayer Nanophotonic Interconnection Network for On-Chip Many-core Communications Xiang Zhang and Ahmed Louri Department of Electrical and Computer Engineering, The University of Arizona 1230 E Speedway
Lecture 12: Interconnection Networks. Topics: communication latency, centralized and decentralized switches, routing, deadlocks (Appendix E)
Lecture 12: Interconnection Networks Topics: communication latency, centralized and decentralized switches, routing, deadlocks (Appendix E) 1 Topologies Internet topologies are not very regular they grew
Topologies. Maurizio Palesi. Maurizio Palesi 1
Topologies Maurizio Palesi Maurizio Palesi 1 Network Topology Static arrangement of channels and nodes in an interconnection network The roads over which packets travel Topology chosen based on cost and
Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation
Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation Kshitij Bhardwaj Dept. of Computer Science Columbia University Steven M. Nowick 2016 ACM/IEEE Design Automation
3D-NoC: Reconfigurable 3D Photonic On-Chip Interconnect for Multicores
D-NoC: Reconfigurable D Photonic On-Chip Interconnect for Multicores Randy Morris, Avinash Karanth Kodi, and Ahmed Louri Electrical Engineering and Computer Science, Ohio University, Athens, OH 457 Electrical
in Oblivious Routing
Static Virtual Channel Allocation in Oblivious Routing Keun Sup Shim, Myong Hyon Cho, Michel Kinsy, Tina Wen, Mieszko Lis G. Edward Suh (Cornell) Srinivas Devadas MIT Computer Science and Artificial Intelligence
3D Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration
IEEE TRANSACTIONS ON COMPUTERS 1 3D Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration Randy W. Morris, Jr., Student Member, IEEE, Avinash Karanth Kodi, Member, IEEE, Ahmed
Ultra-Fast NoC Emulation on a Single FPGA
The 25 th International Conference on Field-Programmable Logic and Applications (FPL 2015) September 3, 2015 Ultra-Fast NoC Emulation on a Single FPGA Thiem Van Chu, Shimpei Sato, and Kenji Kise Tokyo
OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs
OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs 4B-1 Sudeep Pasricha, Shirish Bahirat Colorado State University, Fort Collins, CO {sudeep, shirish.bahirat}@colostate.edu Abstract - Three-dimensional
Lecture 3: Flow-Control
High-Performance On-Chip Interconnects for Emerging SoCs http://tusharkrishna.ece.gatech.edu/teaching/nocs_acaces17/ ACACES Summer School 2017 Lecture 3: Flow-Control Tushar Krishna Assistant Professor
Power and Performance Efficient Partial Circuits in Packet-Switched Networks-on-Chip
2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Power and Performance Efficient Partial Circuits in Packet-Switched Networks-on-Chip Nasibeh Teimouri
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow Abstract: High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture
HANDSHAKE AND CIRCULATION FLOW CONTROL IN NANOPHOTONIC INTERCONNECTS
HANDSHAKE AND CIRCULATION FLOW CONTROL IN NANOPHOTONIC INTERCONNECTS A Thesis by JAGADISH CHANDAR JAYABALAN Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of
NANOPHOTONIC INTERCONNECT ARCHITECTURES FOR MANY-CORE MICROPROCESSORS
NANOPHOTONIC INTERCONNECT ARCHITECTURES FOR MANY-CORE MICROPROCESSORS A Dissertation Presented to the Faculty of the Graduate School of Cornell University in Partial Fulfillment of the Requirements for
Introduction. The fundamental purpose of data communications is to exchange information between user's computers, terminals and applications programs.
Introduction The fundamental purpose of data communications is to exchange information between user's computers, terminals and applications programs. Simplified Communications System Block Diagram Intro-1
Hybrid On-chip Data Networks. Gilbert Hendry Keren Bergman. Lightwave Research Lab. Columbia University
Hybrid On-chip Data Networks Gilbert Hendry Keren Bergman Lightwave Research Lab Columbia University Chip-Scale Interconnection Networks Chip multi-processors create need for high performance interconnects
ACCELERATING COMMUNICATION IN ON-CHIP INTERCONNECTION NETWORKS. A Dissertation MIN SEON AHN
ACCELERATING COMMUNICATION IN ON-CHIP INTERCONNECTION NETWORKS A Dissertation by MIN SEON AHN Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements
Interconnection Network
Interconnection Network Recap: Generic Parallel Architecture A generic modern multiprocessor Network Mem Communication assist (CA) $ P Node: processor(s), memory system, plus communication assist Network
4. Networks. in parallel computers. Advances in Computer Architecture
4. Networks in parallel computers Advances in Computer Architecture System architectures for parallel computers Control organization Single Instruction stream Multiple Data stream (SIMD) All processors
Network-on-chip (NOC) Topologies
Network-on-chip (NOC) Topologies 1 Network Topology Static arrangement of channels and nodes in an interconnection network The roads over which packets travel Topology chosen based on cost and performance
Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects
Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects I. Artundo, W. Heirman, C. Debaes, M. Loperena, J. Van Campenhout, H. Thienpont New York, August 27th 2009 Iñigo Artundo,
Topologies. Maurizio Palesi. Maurizio Palesi 1
Topologies Maurizio Palesi Maurizio Palesi 1 Network Topology Static arrangement of channels and nodes in an interconnection network The roads over which packets travel Topology chosen based on cost and
More is Less, Less is More: Molecular-Scale Photonic NoC Power Topologies
More is Less, Less is More: Molecular-Scale Photonic NoC Power Topologies Jun Pang Department of Computer Science Duke University pangjun92@gmail.com Chris Dwyer Department of Electrical and Computer Engineering
ECE 4750 Computer Architecture, Fall 2017 T06 Fundamental Network Concepts
ECE 4750 Computer Architecture, Fall 2017 T06 Fundamental Network Concepts School of Electrical and Computer Engineering Cornell University revision: 2017-10-17-12-26 1 Network/Roadway Analogy 3 1.1. Running
Interconnection Networks
Lecture 18: Interconnection Networks Parallel Computer Architecture and Programming CMU 15-418/15-618, Spring 2015 Credit: many of these slides were created by Michael Papamichael This lecture is partially
Low-Power Interconnection Networks
Low-Power Interconnection Networks Li-Shiuan Peh Associate Professor EECS, CSAIL & MTL MIT 1 Moore s Law: Double the number of transistors on chip every 2 years 1970: Clock speed: 108kHz No. transistors:
Architectures. A thesis presented to. the faculty of. In partial fulfillment. of the requirements for the degree.
Dynamic Bandwidth and Laser Scaling for CPU-GPU Heterogenous Network-on-Chip Architectures A thesis presented to the faculty of the Russ College of Engineering and Technology of Ohio University In partial
Lecture 25: Interconnection Networks, Disks. Topics: flow control, router microarchitecture, RAID
Lecture 25: Interconnection Networks, Disks Topics: flow control, router microarchitecture, RAID 1 Virtual Channel Flow Control Each switch has multiple virtual channels per phys. channel Each virtual
DSENT A Tool Connecting Emerging Photonics with Electronics for Opto- Electronic Networks-on-Chip Modeling Chen Sun
A Tool Connecting Emerging Photonics with Electronics for Opto- Electronic Networks-on-Chip Modeling Chen Sun In collaboration with: Chia-Hsin Owen Chen George Kurian Lan Wei Jason Miller Jurgen Michel
Interconnection Networks
Lecture 17: Interconnection Networks Parallel Computer Architecture and Programming A comment on web site comments It is okay to make a comment on a slide/topic that has already been commented on. In fact
Meet in the Middle: Leveraging Optical Interconnection Opportunities in Chip Multi Processors
Meet in the Middle: Leveraging Optical Interconnection Opportunities in Chip Multi Processors Sandro Bartolini* Department of Information Engineering, University of Siena, Italy bartolini@dii.unisi.it
TDT Appendix E Interconnection Networks
TDT 4260 Appendix E Interconnection Networks Review Advantages of a snooping coherency protocol? Disadvantages of a snooping coherency protocol? Advantages of a directory coherency protocol? Disadvantages
Optical Interconnection Networks in Data Centers: Recent Trends and Future Challenges
Optical Interconnection Networks in Data Centers: Recent Trends and Future Challenges Speaker: Lin Wang Research Advisor: Biswanath Mukherjee Kachris C, Kanonakis K, Tomkos I. Optical interconnection networks
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 An Inter/Intra-Chip Optical Network for Manycore Processors Xiaowen Wu, Student Member, IEEE, JiangXu,Member, IEEE, Yaoyao Ye, Student
Graphene-enabled hybrid architectures for multiprocessors: bridging nanophotonics and nanoscale wireless communication
Graphene-enabled hybrid architectures for multiprocessors: bridging nanophotonics and nanoscale wireless communication Sergi Abadal*, Albert Cabellos-Aparicio*, José A. Lázaro, Eduard Alarcón*, Josep Solé-Pareta*
Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema
Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema [1] Laila A, [2] Ajeesh R V [1] PG Student [VLSI & ES] [2] Assistant professor, Department of ECE, TKM Institute of Technology, Kollam
Lecture 3: Topology - II
ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 3: Topology - II Tushar Krishna Assistant Professor School of Electrical and
Chapter 4 NETWORK HARDWARE
Chapter 4 NETWORK HARDWARE 1 Network Devices As Organizations grow, so do their networks Growth in number of users Geographical Growth Network Devices : Are products used to expand or connect networks.
Adaptive Routing. Claudio Brunelli Adaptive Routing Institute of Digital and Computer Systems / TKT-9636
1 Adaptive Routing Adaptive Routing Basics Minimal Adaptive Routing Fully Adaptive Routing Load-Balanced Adaptive Routing Search-Based Routing Case Study: Adapted Routing in the Thinking Machines CM-5
BlueGene/L. Computer Science, University of Warwick. Source: IBM
BlueGene/L Source: IBM 1 BlueGene/L networking BlueGene system employs various network types. Central is the torus interconnection network: 3D torus with wrap-around. Each node connects to six neighbours
The Impact of Optics on HPC System Interconnects
The Impact of Optics on HPC System Interconnects Mike Parker and Steve Scott Hot Interconnects 2009 Manhattan, NYC Will cost-effective optics fundamentally change the landscape of networking? Yes. Changes
Prediction Router: Yet another low-latency on-chip router architecture
Prediction Router: Yet another low-latency on-chip router architecture Hiroki Matsutani Michihiro Koibuchi Hideharu Amano Tsutomu Yoshinaga (Keio Univ., Japan) (NII, Japan) (Keio Univ., Japan) (UEC, Japan)
FUTURE high-performance computers (HPCs) and data. Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture
Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture Chao Chen, Student Member, IEEE, and Ajay Joshi, Member, IEEE (Invited Paper) Abstract Silicon-photonic links have been proposed
Design of a high-throughput distributed shared-buffer NoC router
Design of a high-throughput distributed shared-buffer NoC router The MIT Faculty has made this article openly available Please share how this access benefits you Your story matters Citation As Published
Author's personal copy
J. Parallel Distrib. Comput. 68 (2008) 1413 1424 Contents lists available at ScienceDirect J. Parallel Distrib. Comput. journal homepage: www.elsevier.com/locate/jpdc Two proposals for the inclusion of
DCOF - An Arbitration Free Directly Connected Optical Fabric
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 1 DCOF - An Arbitration Free Directly Connected Optical Fabric Christopher Nitta, Member, IEEE, Matthew Farrens, Member, IEEE, and Venkatesh
Synthetic Traffic Generation: a Tool for Dynamic Interconnect Evaluation
Synthetic Traffic Generation: a Tool for Dynamic Interconnect Evaluation W. Heirman, J. Dambre, J. Van Campenhout ELIS Department, Ghent University, Belgium Sponsored by IAP-V PHOTON & IAP-VI photonics@be,
Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip. Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH
Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH Outline Introduction Overview of WiNoC system architecture Overlaid
Performance of coherence protocols
Performance of coherence protocols Cache misses have traditionally been classified into four categories: Cold misses (or compulsory misses ) occur the first time that a block is referenced. Conflict misses
DCAF - A Directly Connected Arbitration-Free Photonic Crossbar For Energy-Efficient High Performance Computing
- A Directly Connected Arbitration-Free Photonic Crossbar For Energy-Efficient High Performance Computing Christopher Nitta, Matthew Farrens, and Venkatesh Akella University of California, Davis Davis,
DESIGN OF A HIGH-SPEED OPTICAL INTERCONNECT FOR SCALABLE SHARED-MEMORY MULTIPROCESSORS
DESIGN OF A HIGH-SPEED OPTICAL INTERCONNECT FOR SCALABLE SHARED-MEMORY MULTIPROCESSORS THE ARCHITECTURE PROPOSED HERE REDUCES REMOTE MEMORY ACCESS LATENCY BY INCREASING CONNECTIVITY AND MAXIMIZING CHANNEL
Extending the LAN. Context. Info 341 Networking and Distributed Applications. Building up the network. How to hook things together. Media NIC 10/18/10
Extending the LAN Info 341 Networking and Distributed Applications Context Building up the network Media NIC Application How to hook things together Transport Internetwork Network Access Physical Internet
A thesis presented to. the faculty of. In partial fulfillment. of the requirements for the degree. Master of Science. Yixuan Zhang.
High-Performance Crossbar Designs for Network-on-Chips (NoCs) A thesis presented to the faculty of the Russ College of Engineering and Technology of Ohio University In partial fulfillment of the requirements
ECE 697J Advanced Topics in Computer Networks
ECE 697J Advanced Topics in Computer Networks Switching Fabrics 10/02/03 Tilman Wolf 1 Router Data Path Last class: Single CPU is not fast enough for processing packets Multiple advanced processors in
NETWORK-ON-CHIPS (NoCs) [1], [2] design paradigm
![NETWORK-ON-CHIPS (NoCs) [1], [2] design paradigm](/thumbs/90/102614410.jpg "NETWORK-ON-CHIPS (NoCs) [1], [2] design paradigm")
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips Dominic DiTomaso,
Designing Chip-Level Nanophotonic Interconnection Networks
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 2, NO. 2, JUNE 2012 137 Designing Chip-Level Nanophotonic Interconnection Networks Christopher Batten, Member, IEEE, Ajay Joshi,
Designing Low-power, Low-latency Networks-on-chip by Optimally Combining Electrical and Optical Links
Designing Low-power, Low-latency Networks-on-chip by Optimally Combining Electrical and Optical Links Sebastian Werner, Javier Navaridas and Mikel Luján The University of Manchester, Manchester, M13 9PL,
CHAPTER 2 - NETWORK DEVICES
CHAPTER 2 - NETWORK DEVICES TRUE/FALSE 1. Repeaters can reformat, resize, or otherwise manipulate the data packet. F PTS: 1 REF: 30 2. Because active hubs have multiple inbound and outbound connections,
Lecture 7: Flow Control - I
ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 7: Flow Control - I Tushar Krishna Assistant Professor School of Electrical
Medium Access Protocols
Medium Access Protocols Summary of MAC protocols What do you do with a shared media? Channel Partitioning, by time, frequency or code Time Division,Code Division, Frequency Division Random partitioning
Network on Chip Architecture: An Overview
Network on Chip Architecture: An Overview Md Shahriar Shamim & Naseef Mansoor 12/5/2014 1 Overview Introduction Multi core chip Challenges Network on Chip Architecture Regular Topology Irregular Topology
Parallel Systems Prof. James L. Frankel Harvard University. Version of 6:50 PM 4-Dec-2018 Copyright 2018, 2017 James L. Frankel. All rights reserved.
Parallel Systems Prof. James L. Frankel Harvard University Version of 6:50 PM 4-Dec-2018 Copyright 2018, 2017 James L. Frankel. All rights reserved. Architectures SISD (Single Instruction, Single Data)
Lecture 24: Interconnection Networks. Topics: topologies, routing, deadlocks, flow control
Lecture 24: Interconnection Networks Topics: topologies, routing, deadlocks, flow control 1 Topology Examples Grid Torus Hypercube Criteria Bus Ring 2Dtorus 6-cube Fully connected Performance Bisection
Ultra-Low Latency, Bit-Parallel Message Exchange in Optical Packet Switched Interconnection Networks
Ultra-Low Latency, Bit-Parallel Message Exchange in Optical Packet Switched Interconnection Networks O. Liboiron-Ladouceur 1, C. Gray 2, D. Keezer 2 and K. Bergman 1 1 Department of Electrical Engineering,
Global Adaptive Routing Algorithm Without Additional Congestion Propagation Network
1 Global Adaptive Routing Algorithm Without Additional Congestion ropagation Network Shaoli Liu, Yunji Chen, Tianshi Chen, Ling Li, Chao Lu Institute of Computing Technology, Chinese Academy of Sciences
CMSC 611: Advanced. Interconnection Networks
CMSC 611: Advanced Computer Architecture Interconnection Networks Interconnection Networks Massively parallel processor networks (MPP) Thousands of nodes Short distance (
Basic Switch Organization
NOC Routing 1 Basic Switch Organization 2 Basic Switch Organization Link Controller Used for coordinating the flow of messages across the physical link of two adjacent switches 3 Basic Switch Organization
Communication has significant impact on application performance. Interconnection networks therefore have a vital role in cluster systems.
Cluster Networks Introduction Communication has significant impact on application performance. Interconnection networks therefore have a vital role in cluster systems. As usual, the driver is performance
PREDICTION MODELING FOR DESIGN SPACE EXPLORATION IN OPTICAL NETWORK ON CHIP
PREDICTION MODELING FOR DESIGN SPACE EXPLORATION IN OPTICAL NETWORK ON CHIP SARA KARIMI A Thesis in The Department Of Electrical and Computer Engineering Presented in Partial Fulfillment of the Requirements
Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-Clockwise Optical Routing
Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-Clockwise Optical Routing Matthew Kennedy and Avinash Karanth Kodi School of Electrical Engineering and Computer Science Ohio University,
Quest for High-Performance Bufferless NoCs with Single-Cycle Express Paths and Self-Learning Throttling
Quest for High-Performance Bufferless NoCs with Single-Cycle Express Paths and Self-Learning Throttling Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan Dept. of Electrical Engineering and Computer
Light Speed Arbitration and Flow Control for Nanophotonic Interconnects
Light Speed Arbitration and Flow Control for Nanophotonic Interconnects Dana Vantrease Univ of Wisconsin - Madison danav@cs.wisc.edu Nathan Binkert HP Laboratories binkert@hp.com Robert Schreiber HP Laboratories
Interconnect Technology and Computational Speed
Interconnect Technology and Computational Speed From Chapter 1 of B. Wilkinson et al., PARAL- LEL PROGRAMMING. Techniques and Applications Using Networked Workstations and Parallel Computers, augmented
Basic Low Level Concepts
Course Outline Basic Low Level Concepts Case Studies Operation through multiple switches: Topologies & Routing v Direct, indirect, regular, irregular Formal models and analysis for deadlock and livelock
EC 513 Computer Architecture
EC 513 Computer Architecture On-chip Networking Prof. Michel A. Kinsy Virtual Channel Router VC 0 Routing Computation Virtual Channel Allocator Switch Allocator Input Ports VC x VC 0 VC x It s a system
WITH THE CONTINUED advance of Moore s law, ever
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 11, NOVEMBER 2011 1663 Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology,
Chapter 9 Multiprocessors
ECE200 Computer Organization Chapter 9 Multiprocessors David H. lbonesi and the University of Rochester Henk Corporaal, TU Eindhoven, Netherlands Jari Nurmi, Tampere University of Technology, Finland University
Thomas Moscibroda Microsoft Research. Onur Mutlu CMU
Thomas Moscibroda Microsoft Research Onur Mutlu CMU CPU+L1 CPU+L1 CPU+L1 CPU+L1 Multi-core Chip Cache -Bank Cache -Bank Cache -Bank Cache -Bank CPU+L1 CPU+L1 CPU+L1 CPU+L1 Accelerator, etc Cache -Bank
An Energy-Efficient Reconfigurable NoC Architecture with RF-Interconnects
2013 16th Euromicro Conference on Digital System Design An Energy-Efficient Reconfigurable NoC Architecture with RF-Interconnects Majed ValadBeigi, Farshad Safaei and Bahareh Pourshirazi Faculty of ECE,
This chapter provides the background knowledge about Multistage. multistage interconnection networks are explained. The need, objectives, research
CHAPTER 1 Introduction This chapter provides the background knowledge about Multistage Interconnection Networks. Metrics used for measuring the performance of various multistage interconnection networks