Understanding the Routing Requirements for FPGA Array Computing Platform. Hayden So EE228a Project Presentation Dec 2 nd, 2003

Transcription

1 Understanding the Routing Requirements for FPGA Array Computing Platform Hayden So EE228a Project Presentation Dec 2 nd, 2003

2 What is FPGA Array Computing? Aka: Reconfigurable Computing Aka: Spatial computing, structural computing A novel way of computing that there is no standard name yet! In short: perform computation not in the von Neumann (stored program) paradigm Explore spatial dimension of computation Provides fine-grain parallelism as well as coarse-grain parallelism We use big array of FPGA to perform computation

3 The Good Old BEE 1 st Generation Built for VLSI design emulation Very traditional But I m aiming at something a lot bigger Not just emulating hw!! General purpose computing

4 The Next Generation: B2 Conceptually a big mesh of FPGA Order of or more FPGAs form a user process Two types of communications between user processes 1. Synchronous data flow Resembles traditional hardware emulation 2. Irregular inter-process communication messages Resembles traditional multi-processor

5 Types of Routing Algorithm Available WAN e.g. Internet Router, BGP, EGRP LAN e.g. Broadcast (ethernet hub, switch) Multiprocessor Network Routing depends on the regular direct network topology Network of Workstation (Cluster) e.g. cluster of LAN connected with high-speed (usually cut-through) switches MANET/Sensor Networks Adhoc network Distributed routing algorithm CAD Routing wires on VLSI Tightly coupled with placement process

6 Routing Synchronous Data Flow Guaranteed data rate Cycle accurate data streams Inherently favors/requires a circuit switch network Variable, but balanced, insertion/startup latency Example: A needs 2 channels to B on a 4-mesh with 1 channels on each side B A Tightly coupled with process placement Very similar to a CAD Place&Route Problem!!! This kind of routing is what FPGA researchers have been doing for the past few decades!! A B

7 Routing Inter-Process Messages Messages passed randomly among different processes For general communication/data transfer/ipc Messages usually divided into packets A packet switch network is an obvious choice Each node is both a processing node and a routing node Consumes packet destined for this node Otherwise forward to neighbors according to routing decision Overall speaking we have a regular topology So we are very similar to a multi-processor network Can we learn something from multi-processor routing?

8 Multi-Processor Routing Basic Major Goals of MPP routing: Performance, Fault Tolerant Performance is key goal Communication cost limits overall performance of parallel algorithms 3 main ideas to obtain low communication cost Regular network typology Wormhole routing Adaptive Routing

9 Regular direct network typology Mesh, Torus, Hyper-Cube, k-ary n-cube Tradeoff network diameter with wire limitation Wants small number of hops (complete graph) I/O limited Relatively easy routing algorithms Spend less time on routing decision e-cube: route in ascending dimension

10 Switching Techniques What s between input & output channels Store-and-Forward Traditional way of packet switch Each packet stored in router, then route Wormhole routing Don t wait for end of packet Route depends on first byte of packet Packet becomes a worm spanning the entire route Store-and-Forward Ref: Ni&McKinley93 Wormhole

11 Adaptive Routing The route a message takes depends on dynamic behavior of network besides source/destination location Very important for Load Balancing Potentially route around network congestion Congestion!! More importantly: Fault Tolerant Can route around fault dynamically

12 Fault Tolerant The ability to operate with some subsets of the nodes/links being nonfunctional Fault tolerance turns out to be extremely important for real life multi-processor system! Parts DO fail Uptime $$ Ex: Boppana&Chalasani 95 Fault tolerant on top of e-cube (4,3) (1,0) (3,0) (3,4)

13 Fault Tolerant vs FPGA Array Routing Fault tolerance turns out to be extremely related to the kind of system we re talking about! Compare the following: They are almost identical!!

14 Wormhole Routing Revisited Recall in wormhole routing a message occupies all buffers along the its route until the message ends Q: What if a message never ends? A: Falls back to circuit-switch! Q: Didn t we mention something about circuit-switch network before? A: Yes, SDF! Seems like we can merge the circuit-switch and packetswitch part of the network into one by carefully crafting wormhole routing algorithm

15 Summary FPGA array routing shares a lot of common properties with multi-processor routings An efficient algorithm can potentially be obtained by modifying existing fault-tolerant mpp routing Wormhole routing can possibly be extended to accommodate the unique requirements for synchronous data flow Still need to address other issues: Scalability Possibility of irregular network typology