Muon Port Card Upgrade Status May 2013

Transcription

1 CSC Endcap Muon Port Card and Muon Sorter Upgrade Status May 2013

2 MPC Upgrade Requirements Be able to deliver all 18 trigger primitives from the EMU peripheral crate to the upgraded Sector Processor Preserve e sorting capabilities of the Muon Port Card Preserve 3 old 1.6Gbps optical links to the existing CSCTF 2

3 Upgrade Developments Use existing Muon Port Card main board - TMB interface remains unchanged (2 LCTs per 80MHz) - 3 old optical links are still available Original design (2004) was based on Xilinx Virtex-E XCV600E FPGA New prototype (2012) is based on Xilinx Spartan-6 FPGA - Inexpensive FPGA ($280 for the fastest speed grade XC6SLX150T-3FFG900C device) - 8 embedded GTP serializers - 3.2Gbps/channel data rate - Modest power consumption (~1A Vccint; <1A GTPs) - Pluggable 12-channel optical transmitter 3

4 New Spartan-6 Mezzanine Top Bottom Pluggable optical transmitter 4

5 Optical Transmitter SNAP12 transmitter Avago AFBR-810 SNAP12 and Avago AFBR-810 are pluggable 12-channel devices Both use the same 10x10 low profile circuit, but pin assignment is different (Avago is intended for higher data rate) utca SP12 uses Avago AFBR820 receiver 5

6 Old and New Mezzanines Installed 6

7 Optical Tests at Rice, Three MPC boards with the new mezzanines SP10 prototype Test software is available, various PRBS and random patterns Random patterns from MPC FIFO to SP10 FIFO under slow VME control: 10K iterations (510 frames each); no errors, all boards PRBS t t OK BER<10 13 PRBS tests OK, BER<10-13 MPC SP10 CCB 7

8 Latency Measurements Present MPC-to-SP system at CMS: 580 ns - TLK2501 Transmitter (1.6Gbps - 80MHz) ~23 ns m optical MMF fiber ~500 ns - TLK2501 Receiver (1.6Gbps - 80MHz) ~57 ns New system (prototypes): 589 ns - Spartan-6 GTP Transmitter (3.2Gbps 160MHz) ~20 ns (without Tx buffer, measured) m optical MMF fiber ~500 ns - Virtex-6 GTX receiver (3.2Gbps 160MHz) ~69 ns (without Rx buffer, estimate) 8

9 Other Measurements Power consumption: - Spartan-6 FPGA ~1A Vccint (1.2V) ~0.15A Vccaux+Vcco (3.3V) ~ 0.8A GTPs (1.2V) - 3 MIC69501 voltage regulators on a mezzanine board passed reactor irradiation test at TAMU in MPC (main board + Spartan-6 mezzanine) 3.3V 3V 9

10 Optical Fibers for P.5 Trunk cable with 4 connectorized cords (similar to one proposed for the DT upgrade). Each cord has 12 fibers. Need 36 cables for 60 peripheral crates, one spare cord per crate. Cable sample was successfully tested at UF in April 2013 Purchase order has been placed through CERN in April

11 Irradiation Tests of the FPGA (1) 66 MeV proton accelerator at Crocker Nuclear Laboratory, UC Davis Wide range of beam fluxes typically from 10 4 to 10 9 p/cm 2 /s 11

12 Irradiation Tests of the FPGA (2) Irradiated with 1 krad at a rate of ~1 Rad/sec (convenient to detect SEU) 75 Single Event Upsets (SEU): 5 to 15 seconds between SEU Average dose to get an error ~13 Rad. With the accumulated fluence of 3*10 11 protons/cm 2, the cross section of SEU is 75 / 3x10 11 = 2.5x10-9 cm 2. Assuming 10-year fluence of ~10 11 neutrons per cm 2 [1] at full LHC design luminosity, the worst case SEU rate would be 2.5x10-9 cm 2 x neutrons/cm 2 / 5x10 7 sec = 5x10-6, or 1 SEU in ~ 55 hours per device [1] Irradiated with 30 krad at a rate 80 Rad/sec (10 years of LHC exposure in the ME1/1 area with a safety factor 3) Many upsets FPGA survived the test Irradiated with 100 krad at a rate of 360 Rad/sec Many upsets FPGA survived the test Irradiated with ~300 Rad at a rate of ~1 Rad/sec again (repeat of first test) 50 SEU in 5 minutes Average dose to get an error ~6 Rad, ~2 times higher than in test 1 FPGA is fully functional 12

13 Irradiation Tests of the EPROM Irradiated with 1 MeV equivalent fluence at ~10.5*10 12 n/cm 2 at the TAMU cyclotron in April 2013 Equivalent to ~30kRad, or 30 years of LHC exposure in ME1/1 area Device was read back; not a single bit change, as expected XCF32P PROM 13

14 What Needs to Be Done in Implement new data format MPC-to-SP - ready for MPC, but not tested with the utca SP Need to set up a test stand at Rice: Track Finder VME crate (exists) - MPC (special slot) - SP05 (to be able to check three old optical links) -CCB - TTCvi/vx New utca crate (exists) - controller (need to be purchased) - AMC13 card (one, currently at UF) - SP12 (from UF) Software to run utca Will need similar test stand at bld.904 at CERN by summer

15 PCB and Parts Mezzanine board: 10-layer PCB Optical transmitter board: 4-layer PCB Xilinx FPGA and EPROM are readily available from stock Optical transmitter: single source (Avago), several weeks delivery other parts not a concern 15

16 Muon Sorter Upgrade Upgraded mezzanine board provides direct optical link to the interim calorimeter trigger 16