Detector interface updates (SVD,ECL,EPID)

Transcription

1 Detector interface updates(svd,ecl,epid) M. Nakao p.1 Detector interface updates (SVD,ECL,EPID) Mikihiko Nakao(KEK-IPNS) December 16, 2010 Belle II DAQ meeting, KEK

2 Detector interface updates(svd,ecl,epid) M. Nakao p.2 We had a series of small meetings with SVD, ECL and EPID experts right after the B2GM W. Ostrowicz (SVD) with Z.A.Liu/H.Xu/M.Nakao A. Kuzmin, V. Zhulanov (ECL) with Z.A.Liu/H.Xu/M.Nakao S. Nishida (EPID) with Z.A.Liu/H.Xu/M.Nakao/R.Itoh/T.Higuchi/Y.Igarashi We identified several unresolved items to be discussed This kind of smaller meetings are more useful than the B2GM parallel sessions

3 Detector interface updates(svd,ecl,epid) M. Nakao p.3 Complaints regarding the tall RJ-45 connectors Tyco has a compact connector, , whose height (9.58mm) is even shorter than a SFP cage (9.65mm) This connector has been used in TT-RX and other PMC cards, and is confirmed to work at 508 Mbps serial links We discussed about a smaller connector (e.g., Molex 2mm pitch connector for the Xilinx JTAG cable), but I d like to stick to RJ-45 if the height is the only concern

4 Detector interface updates(svd,ecl,epid) M. Nakao p.4 on-board clock or distributed clock? if on-board, which frequency? 200 MHz or 125 MHz? ( MHz is not in the discussion) When to decide? SVD needs this info by Christmas Additional comments 200 MHz and 125 MHz case have no common line rate as long as generated from coregen External clock (not from REFCLK pins) is not recommended by Xilinx and cannot be instantiated by coregen wizard, but it is written in the datasheet (UG196) and has been tested to work at several clocks up to MHz (3.125 Gbps line rate)

5 FIFO width and writing clock frequecy? Where to put the RAM buffer? (to be in the Belle2link side) Detector interface updates(svd,ecl,epid) M. Nakao p.5

6 Detector interface updates(svd,ecl,epid) M. Nakao p.6 CDC so far requires 50 8-bit parameters for 48ch IHEP will implement them in their first version of Belle2link SVD s parameters will be set up not through Belle2link ECL is willing to set up parameters through Belle2link including DSP code, it will be up to 20 Mbytes Madatory registers FINESSE has 8 pre-defined mandatory registers including the board type and serial number for each board It would be nice to have a similar set of registers for the frontend boards To store the serial number, an EEPROM would be the best way (part number of protocol to be defined) (not discussed) How to write the front-end register is straighforward. How to read is not trivial.

7 Detector interface updates(svd,ecl,epid) M. Nakao p.7 Zhulanov has been testing the board other than RocketIO I implemented my radiation test firmware, and confirmed that it works The board has MHz Xtal, line rate is Gbps

8 Detector interface updates(svd,ecl,epid) M. Nakao p.8 Virtex5 is now the recommended FPGA for the boards going into the detector ECC (error check and correction) of the configuration memory is possible by additional firmware Tested with a neutron beam To be integrated with the standard package, result with be monitored as a slow control info through optical or timing link Spartan 6 can identify CRC error, but cannot make correction. EPID requires one FPGA (merger) and 4 readout FPGAs per Belle2link. The merger FPGA will be Virtex5, but the readout FPGA may be Spartan6 due to the cost

9 Detector interface updates(svd,ecl,epid) M. Nakao p.9 Belle2link / timing signal physical interface at the frontend readout board version GTP capable FPGA Virtex5 LXT is recommended for SEU sensitive area Pin assignment is partially compatible with Timing Distribution modules of Belle pins to be defined REFCLK Rx Tx moddef[2:0] txfault / rxlos ACK (out) TRG (in) RSV (out) CLK (in) TCK TMS TDI TDO 0.01uF or 0.1uF Xtal FPGA internal pullup may be used for moddef 0.01uF or 0.1uF EEPROM EPSON EG2121 LVDS or PECL Either 125 MHz or 200 MHz, to be decided and may be dropped in the final design SFP Don t make 3-4 and 5-6 pairs! 3ch LVDS LVTTL 1ch LVTTL LVDS (e.g., SN65 LVDT14) for serial number of the board ohm termination is in SN65LVDT14 no AC coupling for JTAG RJ-45 CAT5E (or better) RJ-45 CAT5E (or better) Tyco for space-tight boards jumper to enable / disable remote JTAG function local JTAG programming connector