Creating PCI Express Links in Intel FPGAs

Transcription

1 Creating PCI Express Links in Intel FPGAs Course Description This course provides all necessary theoretical and practical know how to create PCI Express links in Intel FPGAs. The course goes into great depth and touches upon every aspect of the features and functionality of the Hard IP for PCI Express found in Intel devices. The course begins with an overview of PCI Express architecture, then teaches how to build Hard IP for PCI Express design, simulate the design, and debug the design. The course covers PCI Express Gen3 and Gen10 devices as well. Configuration via protocol (CvP) and Partial Reconfiguration over Protocol (PRoP) design flow are also covered. The course continues with the parameter editor in Qsys to customize the Hard IP for a specific hardware and how to connect it to Avalon ST and Avalon MM cores, using DMA between Hard PCIe and on chip memory, and design implementation guidelines. The course ends with introduction of Intel s PCI Express device drivers. The course combines 60% theory with 40% practical work in every meeting. The practical labs cover most of the theory and also include practical digital design. Course Duration 2 days

2 Goals 1. Become familiar with PCI Express architecture 2. Build a Hard IP PCI Express design 3. Simulate a Hard IP PCI Express design using a bus functional model (BFM) 4. Debug a Hard IP PCI Express design 5. Configure an FPGA with a PCI Express design 6. Be familiar with Intel s device driver Intended Users Hardware engineers who develop FPGAs and would like to build a PCI Express design with Intel Hard IP, simulate and debug it. Previous Knowledge FPGA design, VHDL/Verilog, ModelSim, SignalTap Course Material 1. Synthesizer and Place & Route: Quartus Prime 2. ModelSim 3. Course book (including labs) 4. Stratix V FPGA development kit 5. PCIe Passive Adaptive kit

3 Table of Contents Day #1 PCI Express Architecture Overview o PCI Express definition o PCIe generations o PCIe architecture definitions o PCIe components o PCIe layers o Transactions definitions Packet headers Posted vs non posted o Traffic control Routing Completion & configuration Limitations Traffic classes & virtual channels Flow control credits Interrupts o Configuration space Address map Type 0 header (Endpoints) Type 1 header o PCIe Gen3 changes and additional features Building a Hard IP for PCI Express Design o Hard IP for PCI Express features User guides Advantages & benefits of using Hard IP for PCIe Hard IP availability Hard IP features Arria 10 Hard IP enhancements Generation 10 Hard IP protocol stack solutions Hard IP for PCIe IP core variations HIP overview component interface comparison Avalon ST component

4 Avalon MM component Avalon MM with DMA engine PCIe application layer + custom CSRs Configuration bypass mode Single Root I/O Virtualization (SRIOV) Physical function vs virtual function Avalon ST interface with SR IOV IP core Complete PCIe soft IP protocol stack Configuration via Protocol (CvP) using PCIe CvP modes (initialization, update) CvP design flow Partial Reconfiguration over Protocol (PRoP) CvP vs PRoP o Customizing the Hard IP for PCI Express settings Qsys flow and IP catalog flow Customizing the HardIP using the parameter editor o Connecting the Hard IP for PCI Express interfaces Connecting the HIP Avalon ST interfaces RX Avalon ST interfaces signals TX Avalon ST interfaces signals Avalon ST TX Credit interface o Avalon ST cores completion interface TL configuration interface Power management Errors and interrupts Avalon ST Link Management (LMI) Hard IP reconfiguration Link status signals Transceiver reconfiguration Avalon ST ECC error interface Avalon ST interrupt interface Avalon ST interrupts for root ports Avalon ST IP core clocks Data widths and frequencies Reset control & status o Avalon MM component interfaces Transaction interfaces PCI Express => Avalon MM address translation (RX)

5 Avalon MM address => PCI Express address translation (TX) CRA interface Bridge register space o Avalon MM component interfaces with DMA component interfaces Standard interfaces External DMA controller interfaces Embedded DMA controller interfaces o Design implementation.qsys source file Qsys output files Assigning PCI Express transceivers General transceiver arrangement Choose the TX PLL 28 nm channel placement guidelines Aria 10 devices channel placements Gen1/2/3 Input reference clocks Transceiver banks Identifying package pins Assigning pin locations and IO standard Viewing transceivers chip planner Viewing transceivers BluePrint Lab #1: Build a Hard IP for PCI Express Design

6 Day #2 Simulating a Hard IP for PCI Express Design o Hard IP for PCI Express simulation o Design example o Generate Testbench system o PCIe endpoint testbench example o Simulation testbench behavior o Qsys testbench output files o The simulation driver o Locations of the root port driver tasks o Common changes for PCIe simulation o Important PCIe testbench features o Running simulation with the ModelSim tool o Reverse engineering the testbench o Creating your own test case o Example testbench procedures o Chaining DMA testbench example o PCI Express BFM choices Lab #2: Simulate a PCI Express Design Debugging a Hard IP for PCI Express Design o Debugging tools SignalTap II Embedded Logic Analyzer (ELA) Third party PCIe protocol analyzer System console o Debugging hardware bring up Systematic approach Recommended reset sequence Debugging link training Debugging example #1: link fails to reach L0 state Debugging example #2: link hangs in L0 state BIOS enumeration issues Check configuration space Correcting channel loss Gen1/2/3 Design hints for debugging o Debugging link performance

7 PCI Express link performance System block diagram Theoretical system performance Actual PCIe performance measured Factors affecting throughput General debug flow to understand link performance Possible system performance bottlenecks Potential throughput bottleneck and solution Software Drivers o Where Altera s Linux driver fits in the software stack o Where Altera s Windows driver fits in the software stack o Virtualization architecture block diagram overview Lab #3: Debug a PCI Express Design