Advanced ALTERA FPGA Design

Transcription

1 Advanced ALTERA FPGA Design Course Description This course focuses on advanced FPGA design topics in Quartus software. The first part covers advanced timing closure problems, analysis and solutions. The second part covers Qsys tool that is used for building systems in FPGA. The third part covers high speed external memory interfaces design such as DDR3. The fourth part covers FPGA design optimizations such as LogicLock and incremental compilation. The course combines 50% theory with 50% practical work in every meeting. The practical labs cover all the theory and also include practical digital design. At the end of the course FPGA engineers will enhance their skills that needed for complex and high speed designs. Course Duration 8 days Goals 1. Design timing closure methodology like ALTERA experts 2. Analyze and solve timing problems with Quartus II software 3. Efficiently manage device clock resources and PLLs 4. Use TimeQuest advanced features 5. Build a system with Qsys 6. Implement high speed memory interfaces such as DDR3 7. Optimize FPGA design with LogicLock and incremental compilation

2 Intended Users FPGA engineers who would like to enhance their skills and design complex and high speed FPGA projects Previous Knowledge ALTERA FPGAs architecture Quartus II software ModelSim Course Material 1. Simulator: Modelsim 2. Synthesizer and Place & Route: Quartus II 3. ALTERA Evaluation board 4. Course book (including labs) Table of Contents Timing Closure Day #1-2 Timing Reports Review o Reporting settings o Reporting in TimeQuest o Most useful reports o Report timing: show routing o Detailed slack/path report o Report exceptions o Timing closure recommendations Recommended Methodology for Timing Closure o Setting expectations o Timing failure analysis flow o Working with messages

3 o Common timing constraint issues o Effect of incorrect timing constraints o Design assistant o Timing optimization advisor o Global and individual speed optimizations o Physical synthesis types o Asynchronous control signals and pipelining o Timing driven compilation (TDC) o Optimize hold timing o I/O optimizations o Report timing approaches o Evaluate results Analyzing & Solving Timing Failures o Using the chip planner o Cross-probe from TimeQuest o Shows delays and physical routing o Viewing routing congestion o Viewing high-speed and low-power tiles o Solutions for too many logic levels o Solutions for high fanout signals o Solutions for conflicting assignments o Solutions for tight timing requirements o Solutions for clock crossing timing failures o Solutions for clock skew The Fitter, Seeds & DSE o Fitter settings per architecture o Seeds and seed sweeping o The Magic seed o Seed sweep: monitoring a change o Design Space Explorer (DSE) o Exploration spaces o Recommendations using DSE Resource Utilization o What affects timing closure? o Logic utilization o Clustering difficulty o Interconnect utilization o Compile time o Interconnect & hold time o Repeatability o Balance hard/soft resource use Understanding Device Clocking Resources o Timing closure & clocking resources o Hierarchical clocking resources o Global clocks (GCLK) o Regional clocks (RCLK) o Peripheral clocks (PCLK) o Section clocks (SCLK)

4 o PLL o Clock control blocks o Utilizing global routing resources o Tradeoffs when using clock buffer o Resets and global networks Additional Timing Closure Topics o Close timing through over-constraining o Incremental compilation o Timing closure in Qsys systems o Common clock path pessimism removal (CCPP) o Synthesis netlist optimizations o Early timing estimate Day #3-4 Advanced Timing Analysis with TimeQuest SDC Review o Collections o Clock & I/O constraints o Timing exceptions Timing Analysis and Tcl o Quartus II executables & Tcl packages o Timing analysis Tcl packages o Running TimeQuest from command line o Running timing analysis during flow o SDC and Tcl examples Timing Exceptions o Most common multicycle use cases o Determining and applying multicycles o Examples for multicycle setup and multicycle hold o Verify multicycle with TimeQuest o Exception priorities o Clock enable with multicycle o Why standard SDC cpllections do not work o get_fanouts (Altera SDC extension) Constraining Source Synchronous Interfaces (SDR, DDR) o Source synchronous interfaces overview SDR center aligned clock SDR edge aligned clock Data captured on same edge Data captured on opposite edge o SDR input interface constraints Virtual clocks

5 Direct clocking: center aligned data PLL clocking: center aligned data PLL clocking: edge aligned data o Data input timing constraints Tco relative to input & output clock Input delay: setup/hold provided Input delay: center aligned Input delay: edge aligned Specification provides skew o SDR output interface constraints Common data and output clock PLL generated clock output DDIO registers Data output timing constraints Skew output constraints Output clock false path Edge aligned output multicycle exception DDIO output false path exception SDR analysis in TimeQuest o Source synchronous DDR interfaces Double data rate complexities DDR input and output logic o DDR input interface constraints Input clock 90 o phase shift Setting DDR input delay constraints o Timing exceptions for DDR inputs Same edge transfer Opposite edge transfer Using tsu/th requirements o DDR output interface constraints PLL generated clock output Toggling clock output register Setting output delay constraints Timing exceptions for DDR outputs Same edge transfers Opposite edge transfers Output clock false path Output constraints using skew o DDR analysis Output rising-edge setup/hold timing reports Feedback Designs o Clock feedback Required constraints Clock feedback example o Data feedback Required constraints Data feedback example Combined feedback techniques LVDS Timing Analysis (optional) o LVDS hardware o LVDS transmitter o Transmitter report

6 o Transmitter channel-to-channel skew (TCCS) o LVDS receiver o Dynamic Phase Alignment (DPA) o Non-DPA interface o Dedicated SERDES analysis (non-dpa) o Key LVDS specifications Time unit interval (TUI) Receiver sampling window (SW) Transmitter channel-to-channel skew (TCCS) Receiver channel-to-channel skew (RCCS) Receiver skew margin (RSKM) LVDS equation Three ways to use RSKM Constraining for link success example o Data receiver modes DPA/soft-CDR mode analysis Day #5 Introduction to the Qsys System Integration Tool What is Qsys? o Traditional system design o Automatic interconnect generation o Qsys benefits o Target Qsys applications o Qsys vs SOPC Builder o SOPC Builder systems in Qsys Qsys UI o Component library o System contents o System inspector o Address map o Clock settings o Project settings o Generation o HDL example o Messages o Other useful Qsys commands Using Qsys in FPGA Design Flow o FPGA hardware design flow o Additional Qsys verification support o Qsys system generation Qsys Files o Qsys source files

7 o Qsys output files Introduction to Qsys Interconnect o Qsys interconnect architecture o Qsys supported standard interfaces (Avalon, AXI) o Qsys interconnect implementation o Arbitration priority o Enables simultaneous multi-mastering o Qsys memory-mapped packet format o Packetized interconnect vs latency o NoC architecture o Master network interface o Slave network interface o Pipelining Using Qsys IP o Qsys standard interfaces for IP Clock Reset Avalon-ST Avalon-MM Avalon-C Avalon-TC AXI o Qsys IP Component library parameter editors Basic components Streaming components Memory components Tristate components Bridge components High-speed interface components Processor components Creating Custom Components o Custom components interconnect o Example custome components o Component editor Processor Interfaces o Interfacing FPGA with external processors o Memory mapped interface o High-speed serial interfaces o Good use of SPI/Avalon master bridge o Using the NIOS II processor o Using the SoC devices

8 Day #6-7 Implementing, Simulating & Debugging External Memory Interfaces Introduction to Altera s Memory Solutions o Current common memory interfaces o Memory selection criteria o ALTERA FPGAs support multiple interface types DDR3 Memory & Implementation o DDR3 memory basics o DDR3 leveling (read/write) o Component/DIMM implementation options DDR Logic Implementation in Altera FPGAs o Memory implementation in FPGAs o Cyclone V devices o Aria V devices o Stratix V / Arria V GZ devices o Example DQ/DQS block o FPGA external memory support & maximum supported frequencies Altera High-Speed Memory Interface IP o High performance controller II (HPC) o UniPHY o Multi-port front end (MPFE) Memory Interface Design Flow o Recommended memory interface design flow o Parameterize with the MegaWizard Plug-In Manager o Quartus II project settings Functionality and Simulation of a Memory System o Controller operation and connection to user logic o Performing a simulation Board and Termination Considerations o Assigning I/O constraints o Termination settings and options Timing Analysis o Timing components o Timing closure DDR2/3 Controllers with UniPHY EMIF Toolkit o Enabling communication via CSR port

9 o EMIF toolkit o Calibration troubleshooting Memory Interfaces with a NIOS II Processor and Qsys o Accessing memory from NIOS II processor o Qsys systems o Memory IP in Qsys o Example design in Qsys Multiple Memory Controllers in a Single FPGA o Multiple memory interfaces o Creating multiple memory controllers o DLLs in Stratix FPGAs o PLL/DLL/OCT sharing o Example of full resource sharing o Stratix V multiple interface guidelines o Efficiently fitting memory interfaces Day #8 Design Optimization Using Incremental Compilation & LogicLock An Introduction to Incremental Compilation o Top-down design flow o Single project design flow issues o Team based design flow issues o Incremental compilation definition o Compilation flow o How incremental compilation works o Considering FPGA design trade-offs o Setting expectations o When not to use incremental compilation o Planning considerations Design Partitions o What are design partitions? o Partition recommendations o Design planning o Design guidelines Design Partition Tools & Interface o Creating design partitions o Design partitions window o Partition netlist types o Fitter preservation levels o Design partition properties o Assessing partition quality

10 o Design partition planner o Chip planner Design Partition Tips and Techniques o Quick multi-partition top-level file o Creating black-box wrapper files o Use empty partition resources for debugging o Fast compiles with SignalTap II o Partition I/O interfaces (DDR3, PCIe,RapidIO) o Timing closure with incremental compilation o Hierarchy isolation o Strategy for maximizing performance LogicLock Regions and Floorplanning o Physical partitioning o Why floorplan is important o Floorplan based on design o Analyze the unfloorplanned fit o Early ve late floorplan LogicLock Region Tools o Defining LogicLock regions o LogicLock region types o LogicLock regions window o Reserved regions o Excluded elements o Region properties o Creating non-rectangular regions o Parent & children regions o Assigning logic to region o Placement of LogicLock regions o LogicLock region resources Floorplanning Tips and Strategies o Create floorplan o Early timing estimate (ETE) o Assigning regions manually o Creating a late floorplan o Floorplan recommendations Single and Multi-Project Design Flows o Top-down flow o Team-based flow Restrictions and Limitations