The 3D-Memory Evolution

Transcription

1 The 3D-Memory Evolution ISC 2015 /, Director Marcom + SBD EMEA

2 Legal Disclaimer This presentation is intended to provide information concerning computer and memory industries. We do our best to make sure that information presented is accurate and fully up-to-date. However, the presentation may be subject to technical inaccuracies, information that is not up-to-date or typographical errors. As a consequence, Samsung does not in any way guarantee the accuracy or completeness of information provided on this presentation. Samsung reserves the right to make improvements, corrections and/or changes to this presentation at any time. The information in this presentation or accompanying oral statements may include forward-looking statements. These forward-looking statements include all matters that are not historical facts, statements regarding Samsung Electronics' intentions, beliefs or current expectations concerning, among other things, market prospects, growth, strategies, and the industry in which Samsung operates. By their nature, forwardlooking statements involve risks and uncertainties, because they relate to events and depend on circumstances that may or may not occur in the future. Samsung cautions you that forward looking statements are no guarantees of future performance and that the actual developments of Samsung, the market, or industry in which Samsung operates may differ materially from those made or suggested by the forward-looking statements contained in this presentation or in the accompanying oral statements. In addition, even if the information contained herein or the oral statements are shown to be accurate, those developments may not be indicative developments in future periods.

3 Business Portfolio Samsung Electronics

4 Samsung Memory More Speed. Less Energy.

5 The Density / Bandwidth / Performance Challenge Stacked DRAM is needed to meet density requirements due to slow scaling TSV 3DS DRAM can meet both high density and speed requirements Slowdown in Capacity Growth Rate Perf. Limitation of Conv. Stack Tech. Module Density 32GB Introduction 64GB Introduction Yearly Speed Requirement [Mbps] Speed Requirement 2993 DRAM Density Gb 8Gb Gb 32GB= 2Gb 4stack 4Gb 2stack 64GB= 4Gb 4stack 8Gb 2stack 2133 DDP Speed Limit

6 Samsung TSV 3DS Technology for Next Gen. DRAM TSV 3DS is stacked DRAM dies with Through-Silicon-Via connections Conventional Stack Solutions <QDP Wire-bond Package> TSV Solutions <4H TSV Package> RDL 2) Wire-Bond Slave Chip Master Chip TSV VIA <QDP LRDIMM> <3DS TSV RDIMM> Memory Controller Data Buffer DRAM Memory Controller Integrated Buffer Less I/O power DRAM (Master) Number of loading limits high speed operations Only master chip communicates with controller regardless of number of stacking 6 / 16 1) 3DS: 3 Dimensional Stack 2) RDL: Re-Distribution Layer

7 *3DS TSV DRAM More Bandwith at High Densities Conventional Stack DRAM 3DS 4H DRAM (TSV) Improved Turn-around Time I/O buffer on DIMM causes inefficiencies Seamless Read/Write among DRAMs Improved Bandwidth Mbps DDP Speed Limit Mbps Ability to follow upcoming requirements 9.9W Improved Energy Efficiency DIMM power for 1 DIMM per channel 7.5W DIMM power for 1 DIMM per channel

8 System Power[Watt] System Power Bandwidth[GB/s] PoC Results with Real-world HPC Servers and Workloads Lenovo-Samsung-SAP carried out PoC and DDR4 3DS TSV RDIMM consumes 30% less power than DDR3 QDP LRDIMM in SAP HANA scenario ATOS-Samsung PoC demonstrates that DDR4 3DS TSV RDIMM provides 36% more bandwidth at 27% less power consumption Lenovo-Samsung-SAP PoC ATOS-Samsung PoC High-Volume Order-to-Cash SAP S/4HANA Scenario 25M memory allocation/de-allocation, Memory Speed 1333Mbps* DDR4 3DS RDIMM 1600 (POR+1) DDR4 3DS RDIMM 1333 (POR) DDR3 QDP LRDIMM 1066 (POR) Time DDR4 3DS HSW(CPU 50%) DDR3 QDP IVB (CPU 80%) DDR3 QDP HSW (CPU 50%) -Haswell-EX Server, 4 CPU, 96DIMMs *DDR3 LRDIMM POR speed is 1066Mbps Measurements were obtained on a 4 socket systems with 96 DIMMs of 64GB capacity

9 High Bandwidth TSV DRAM Solution HBM Memory Bandwidth HBM is TSV stacked DRAM with a silicon interconnect to the processor High bandwidth through a wide data bus, enabled by TSV and a Silicon Interposer HBM and Bandwidth Requirement 300 [GB/s] HBM(High Bandwidth Memory) Buffer-die(Logic)+Core-die(DRAM) Processor DRAM Logic Si Interposer DDR3/4, WIO HBM GDDR5 HBM x4ea (1TB/s, 2Gbps) GDDR5 x12ea (384GB/s, 8Gbps) Bandwidth and Power Gains [GB/s] 17,1 19, DDR3 DDR4 GDDR5 GDDR5 HBM [(GB/s)/Watt] GDDR5 5Gbps Bandwidth Trend HBM Enables Bandwidth of 512GB/s Bandwidth/Power GDDR5 6Gbps 1.8x higher 1.9x higher HBM

10 A complete SSD Lineup for every Task Adapted to different workloads and all in 3D V-NAND: SATA SAS PCIe High End DB / Application Server Cloud Server, Storage SM863 PM1635 PM1725 Main Stream CDN, VoD, Web, File Server PM863 PM1633 PM953

11 LP-NVMe SSD For Big Data and Hyperscale Needs SAMSUNG low power NVMe SSD is widely deployed in hyperscale data centers and big data analytics systems NVMe SSD vs. SATA SSD 480/960/1920 GB IOPS SATA SSD NVMe SSD 1.9 x Higher 3.2 x Higher High Performance (SM953- Seq. R/W: 1.75/0.85 GB/s) Low Active Power < 8W Database OLTP Decision Support System

12 Ultra Highend Performance: Enterprise Class NVMe SSD World 1 st NVMe in 2014 and 2 nd gen. NVMe was released early this year SAMSUNG NVMe SSD demonstrates ultra low latency and high performance The Benefits of NVMe SSD Low Latency High Performance 1.6/3.2/6.4TB SAS SSD NVMe SSD 2.1 x Faster 4 x Higher 3.4 x Higher World 1 st NVMe SSD in 2014 High Performance (SM1715- Seq. R/W: 3/2.2 GB/s) Affordable Endurance by V-NAND Latency Ran. Read Ran. Write

13 Thank you for your attention!