Future Memories. Jim Handy OBJECTIVE ANALYSIS

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2 Future Memories Jim Handy OBJECTIVE ANALYSIS

3 Hitting a Brick Wall OBJECTIVE ANALYSIS

4 Panelists Michael Miller VP Technology, Innovation & Systems Applications MoSys Christophe Chevallier VP NVM/Storage Division Rambus Jim Lipman Director of Marketing SiDense Bill Gervasi Memory Technology Analyst Discobolus Designs OBJECTIVE ANALYSIS

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6 Christophe Chevallier Rambus Inc. September 18, Rambus Inc. 1

7 Future Memories RRAM, MRAM, PCM, 2 terminal bit-cells Small arrays Parallelism high speed read and write Low power Smaller write amplification at system level Adapt to new specs: Not a DRAM replacement: endurance is limited NAND replacement: better endurance, faster latency and through-put only after integration issues are resolved 2012 Rambus Inc. 7

8 High Density, Small Arrays, Low Power, High Bandwidth Low Power Tb Memory, High System Bandwidth High Speed Interface WL Control Gain Stage Sensing Byte / Page Erase RRAM cell in a cross point for very high density NAND: Few massive arrays RRAM: Numerous memory tiles Stackable Cross-Point Hierarchical BL Low Current Cell Vertical Processing Small Arrays / Parallelism Self-select (no select transistor) 4096b I/O 8kB Page Buffer 4096b 4096b 4096b 4096b 4096b 4096b I/O 8kB Page Buffer (+5) 64kb (+5) 4096b 4096b 4096b 4096b 4096b 4096b 1x 1x 1x 1x 1x 1x 16x 2012 Rambus Inc. 8

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10 The Search for a Universal Memory Jim Lipman Marketing Director, Sidense MemCon Future Memories Panel September 18 th, 2012 Copyright 2012 Sidense Corp. All rights reserved.

11 Wanted A Universal Memory The speed of SRAM, density of DRAM, and non-volatility of Flash and ROM Standard CMOS process nothing added, low cost Low power, fast access, long retention Supports high densities, large capacities Very scalable with process shrinks Several upcoming technologies are close (but no cigar) Copyright 2012 Sidense Corp. Page 11 The Future of Logic NVM TM

12 There is no Magic Bullet yet Chips will continue to use multiple memory technologies for the foreseeable future In addition to RAM and Flash/MTP, add antifuse 1T-OTP a viable alternative for OTP and MTP memory in many applications Challenges will remain: smaller geometries, leakage, power consumption, materials Copyright 2012 Sidense Corp. Page 12 The Future of Logic NVM TM

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14 Future of (Networking) Memory Michael J. Miller VP Technology Innovation & Systems Applications

15 Foundations of Our Industry Scaling as a result of: Smaller features Larger wafers & fabs Smaller voltages Scaling allows more for same price in the same or smaller package More features, bandwidth, & storage Challenges ahead as a result of continued scaling: World is not shrinking Effective distance /latency increasing Pushing quantum scale limits of Si and light statistical results Testing & imputed reliability Power! 2012 MoSys, Inc. 15

16 Cross Road Splits at the Chip & Package Edges Parallel I/O 2.4G 3.2G 1 pwr pin per 2 I/O pins 50 mm Memory Memory SoC w/memory Organic package substrate: 2500 balls ~1K to 1.5K I/O Serial I/O: 15G 28G 1 pwr pin per 1 I/O 26 mm Memory Memory Memory SoC Smart Memory Known Good Die vs None Good Die 32 mm 50 mm 2.5D Silicon interposer: >25K bumps 2012 MoSys, Inc. 3

17 Intelligent Error Management Required BIST & Self-Repair Take lessons from nature self healing Moves intelligence from test floor to on die resources Latent Defects In package repair Test and post reflow and post final-assembly Enables KGD for leading process nodes Dealing with Field Errors Soft Errors Noise induced, Cosmic or terrestrial neutrons Channel Errors Reliable transport: GigaChip Interface VRT: The Memory Test Escape You Can't Escape From! Craig Soldat, Cisco 2012 Silicon Valley Test Conference Though VRT is better understood today no strategies have come forward to eliminate the flaws in the silicon gate structures which cause the VRT behavior or reliably screen for the behavior in production MoSys, Inc. 17

18 Smart, Intelligent Accesses ingress Multi-threaded Multi-Cores allow for high processing throughput Multi-bank Multi-partitions allow for high access availability Allows Extended Carrier Class & In package Repair BIST Selfrepair 0 1 Serial Link Serial Link Packet Processor Multi-cycle Scheduler ALU n-1 n Serial Link Serial Link Bandwidth Engine 2013 Q1: 12 GOp/s 4.5 GA 384 Gb/s egress Multi-linked allow for concurrent transport operations ALU for functional Acceleration Local processing minimizes intra-chip traffic 2012 MoSys, Inc. 18

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20 D ISCOBOLUS ESIGNS DRAM Future Perspectives Are We Out of Gas? Bill Gervasi September 18, 2012

21 Current Lay of the Land CPU CPU CPU Unbuffered Registered Load Reduced CPU Each solution has tradeoffs regarding frequency, latency, and capacity Solder Down 21

22 Memory Chips & Stacks Classic window BGA Dual Face Down DDP RDL DDP 3DS with through silicon vias 22

23 Roadblocks Socket is the limiting factor, capacity req low Move to solder down UDIMM loading prevents address bus from getting better Move applications to RDIMM RDIMM loading prevents data bus from getting better Move applications to LRDIMM LRDIMM loading prevents capacity from getting better Move to memory hubs 23

24 Memory Hub Hub CPU 24

25 Combined Hub & 3DS Hub Inherits problems from the FB-DIMM generation SERDES run hot SERDES increase latency Minimum silicon size for hub is pretty large Must incorporate the entire controller ECC, sparing, refresh, etc. Political battle to hand over control to suppliers? 25

26 Summary Current DDR4 roadmap carries us from 2014 through 2020 Application upscaling extends life years Hubs or solder down delay need for stacking 10 years or more to figure out how to yield 3DS 26

27 Thank You Bill Gervasi Discobolus Designs

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