Nios Soft Core. Development Board User s Guide. Altera Corporation 101 Innovation Drive San Jose, CA (408)

Transcription

1 Nios Soft Core Development Board User s Guide Altera Corporation 101 Innovation Drive San Jose, CA (408)

2 Nios Soft Core Development Board User s Guide Version 1.1 August 2000 Altera, AMPP, APEX, APEX 20K, Atlas, BitBlaster, ByteBlaster, ByteBlasterMV, MAX+PLUS II, MegaCore, MegaLAB, OpenCore, Quartus, SignalTap are trademarks and/or service marks of Altera Corporation in the United States and other countries. Product design elements and mnemonics used by Altera Corporation are protected by copyright and/or trademark laws. Altera Corporation acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, including the following: Verilog is a registered trademark of Cadence Design Systems, Incorporated. IBM and AT are registered trademarks and IBM PC-AT is a trademark of International Business Machines Corporation. Microsoft is a registered trademark and Windows is a trademark of Microsoft Corporation. Altera reserves the right to make changes, without notice, in the devices or the device specifications identified in this document. Altera advises its customers to obtain the latest version of device specifications to verify, before placing orders, that the information being relied upon by the customer is current. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty. Testing and other quality control techniques are used to the extent Altera deems such testing necessary to support this warranty. Unless mandated by government requirements, specific testing of all parameters of each device is not necessarily performed. In the absence of written agreement to the contrary, Altera assumes no liability for Altera applications assistance, customer s product design, or infringement of patents or copyrights of third parties by or arising from use of semiconductor devices described herein. Nor does Altera warrant or represent any patent right, copyright, or other intellectual property right of Altera covering or relating to any combination, machine, or process in which such semiconductor devices might be or are used. Altera products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Altera Corporation. As used herein: 1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Products mentioned in this document are covered by one or more of the following U.S. patents: 5,892,683; 5,880,725; 5,880,597; 5,880,596; 5,878,250; 5,875,112; 5,873,113; 5,872,463; 5,870,410; 5,861,760; 5,859,544; 5,850,365; 5,850,152; 5,850,151; 5,848,005; 5,847,617; 5,845,385; 5,844,854; 5,835,977; 5,838,628; 5,838,584; 5,835,998; 5,834,849; 5,828,229; 5,825,197; 5,821,787: 5,821,773; 5,821,771; 5,815,726; 5,815,024; 5,815,003; 5,812,479; 5,812,450; 5,809,281; 5,809,034; 5,805,516; 5,802,540; 5,801,541; 5,796,267; 5,793,246; 5,790,469; 5,787,009; 5,771,264; 5,768,562; 5,768,372; 5,767,734; 5,764,583; 5,764,569; 5,764,080; 5,764,079; 5,761,099; 5,760,624; 5,757,207; 5,757,070; 5,744,991; 5,744,383; 5,740,110; 5,732,020; 5,729,495; 5,717,901; 5,705,939; 5,699,020; 5,699,312; 5,696,455; 5,693,540; 5,694,058; 5,691,653; 5,689,195; 5,668,771; 5,680,061; 5,672,985; 5,670,895; 5,659,717; 5,650,734; 5,649,163; 5,642,262; 5,642,082; 5,633,830; 5,631,576; 5,621,312; 5,614,840; 5,612,642; 5,608,337; 5,606,276; 5,606,266; 5,604,453; 5,598,109; 5,598,108; 5,592,106; 5,592,102; 5,590,305; 5,583,749; 5,581,501; 5,574,893; 5,572,717; 5,572,148; 5,572,067; 5,570,040; 5,567,177; 5,565,793; 5,563,592; 5,561,757; 5,557,217; 5,555,214; 5,550,842; 5,550,782; 5,548,552; 5,548,228; 5,543,732; 5,543,730; 5,541,530; 5,537,295; 5,537,057; 5,525,917; 5,525,827; 5,523,706; 5,523,247; 5,517,186; 5,498,975; 5,495,182; 5,493,526; 5,493,519; 5,490,266; 5,488,586; 5,487,143; 5,486,775; 5,485,103; 5,485,102; 5,483,178; 5,477,474; 5,473,266; 5,463,328, 5,444,394; 5,438,295; 5,436,575; 5,436,574; 5,434,514; 5,432,467; 5,414,312; 5,399,922; 5,384,499; 5,376,844; 5,375,086; 5,371,422; 5,369,314; 5,359,243; 5,359,242; 5,353,248; 5,352,940; 5,309,046; 5,350,954; 5,349,255; 5,341,308; 5,341,048; 5,341,044; 5,329,487; 5,317,212; 5,317,210; 5,315,172; 5,301,416; 5,294,975; 5,285,153; 5,280,203; 5,274,581; 5,272,368; 5,268,598; 5,266,037; 5,260,611; 5,260,610; 5,258,668; 5,247,478; 5,247,477; 5,243,233; 5,241,224; 5,237,219; 5,220,533; 5,220,214; 5,200,920; 5,187,392; 5,166,604; 5,162,680; 5,144,167; 5,138,576; 5,128,565; 5,121,006; 5,111,423; 5,097,208; 5,091,661; 5,066,873; 5,045,772; 4,969,121; 4,930,107; 4,930,098; 4,930,097; 4,912,342; 4,903,223; 4,899,070; 4,899,067; 4,871,930; 4,864,161; 4,831,573; 4,785,423; 4,774,421; 4,713,792; 4,677,318; 4,617,479; 4,609,986; 4,020,469 and certain foreign patents. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Copyright 2000 Altera Corporation. All rights reserved.

3 Table of Contents Features...1 APEX EP20K200E...2 Memory...2 SRAM...3 Flash Memory...3 SDRAM...3 Configuration Controller...4 Daughter Cards...4 SDRAM SODIMM Socket...5 PMC Connectors...5 JTAG Circuit...5 Power Supply...6 Serial Port...7 Switches and Other Features...7 SW1: User-Specific Functions...7 SW2: Reset Function...8 SW3: Clear Function...8 SW4 - SW7: User-Specific Functions...8 LEDs...8 Clocks...9 i

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5 Features The Nios Development Board (see Figure 1 on page 2) has the following features: One APEX EP20K200E device (U1) Two 1 Mbit (64K x 16) SRAM devices (U14, U15) One MAX7064PLD (U4) Factory programed as configuration controller Configures APEX device from flash data One 8Mbit (512K x 16) flash memory device (U9) One serial-port connector (J3) and RS-232 level-shifter (U13) One JTAG connector (JP3) for device programming and debugging Three switches (SW8, SW9, SW10) connecting the configuration controller, APEX EP20K200E device, and the PCI mezzanine card (PMC) peripheral to the JTAG chain Four user-definable push button switches (SW4, SW5, SW6, SW7) One user-definable 8-bit DIP switch block (SW1) SDRAM SODIMM socket (J2) Two PMC connectors (IEEE-1386 JN1 and JN2) Headers for prototype daughter 3.3 volts (JP8, JP9, JP10) 5.0 volts (JP11, JP12, JP13) Two special-purpose push button switches (defined by the default configuration): Reset (SW2): Clears the APEX EP20K200E device and reloads from configuration controller Clear (SW3): Clears the embedded processor (CPU reset) Four LEDs: Two user-definable LEDs (LED1, LED2) Two special-purpose LEDs: power and flash_byte (LED7, LED3) One 2-digit 7-segment LED (D1) Power supply circuitry (+9V unregulated input, center-negative J1) 1

6 Development Board User s Guide Figure 1. Development Board LED7 TP1 LED1 LED2 SW2 SW3 SW1 TP2 JP11 J1 SW7 SW6 SW5 SW4 JP2 SW10 SW9 JP3 SW8 JP12 JP13 PMCJN2 PMCJN1 $ 3 ( ; EP20K200E JP8 J3 JP14 J2 LED3 JP9 JP10 TP4 APEX EP20K200E The Nios Development Board has one APEX EP20K200EFC484 device, which you can use to configure and evaluate a Nios embedded processor. Memory The Nios Development Board has two 64K x 16 SRAM devices, one 8- Mbit flash memory device, and 144-pin SODIMM memory expansion socket. 2

7 SRAM The two 64K x 16 SRAM devices may be configured for use with either 16- bit (64K x 16) or 32-bit (64K x 32) applications. Because of the addressing limitations, the Nios 16-bit processor may only access a single SRAM. To use both SRAM chips as a single bank of 32-bit wide memory, the A1/ A17 signal is used as A17 and sram1_cs should be asserted coincident with sram0_cs. To use the SRAM as two individual banks of 16-bit words, the A1/A17 signal is used as A1 and BE#2 and BE#3 should be used as BE#0 and BE#1 for sram1. Flash Memory The Nios Development Board contains one 512K x 16 (AM29LV800B) flash memory device. The APEX EP20K200E device and the Nios embedded processor share the flash memory. Flash memory allocation is listed in Table 1. Table 1. Flash Memory Allocation Flash Address Size Comments 0x1C0000 0x1FFFFF 256 KByte Factory-default APEX configuration See Configuration Controller on page 4. 0x x1BFFFF 256 KByte User-defined APEX configuration data 0x x17FFFF 512 KByte Nios instruction and nonvolatile data space SDRAM The Nios Development Board contains a 144-pin SODIMM socket that holds single-data-rate, 64-bit, SDRAM modules. The signals routed to the SODIMM socket are connected to normal APEX I/O pins, and may be configured to the user s unique application. (See SDRAM SODIMM Socket on page 5. for more details.) 3

8 Development Board User s Guide Configuration Controller The MAX7064 device (U4) is factory programed as a configuration controller. The configuration controller loads configuration data from the flash (U3) and clocks it into the APEX device (U1). User-created configurations are loaded by shorting JP2; the factory default configuration is loaded by leaving JP2 open. The configuration controller is started by the rising edge of reset#. Pressing the Reset button (SW2) forces reset# low. The outputs of the configuration controller are placed into a high-impedance state when configuration and initialization are complete. 1 Although the configuration controller is accessible and programmable from the JTAG chain, Altera does not recommend that you reprogram the configuration controller. Reprogramming the configuration controller may result in an inoperable board. Daughter Cards A daughter card may be connected to Nios Development Board. The Nios Development Board supports the connection of either a 3.3 volts or 5.0 volt daughter card. Headers JP11, JP12 and JP13 support the 5.0 volt daughter card; headers JP8, JP9 and JP10 support the 3.3 volt daughter card. The Nios Development Board includes the necessary circuitry to accommodate the 5.0 volt daughter card signals and regulated 3.3 and 5.0 volt power (500 milliwatts). The Altera daughter card interface also accommodates user-specific designs. Refer to accompanying Nios Development Board schematics for specific pinout and interface details. 4

9 SDRAM SODIMM Socket The Nios Development Board provides a 144-pin SODIMM socket to support single-data-rate, 64-bit, SDRAM SODIMM modules. The SDRAM controller for the SODIMM socket can be either an Altera intellectual property (IP) or user-devised logic residing in the APEX device. The signals routed to the SODIMM socket are compliant with those required to support a SDRAM module. With the exception of ground, power and clock pins, the connector pins are connected to normal APEX I/O pins, and may be configured to whatever application the user wishes. (Refer to the schematic for pinouts.) PMC Connectors The Nios Development Board provides two PMC connectors (JN1 and JN2) that conform with the IEEE Std specification for Common Mezzanine Card. JTAG Circuit The Nios Development Board has a standard JTAG header (JP3) for use with the MasterBlaster or ByteBlasterMV cables. Each of the three devices in the JTAG chain may be connected or disconnected by using switch SW8, SW9 or SW10. These switches control the connection of the APEX EP20K200E device, the configuration controller, and the PMC connector, respectively. 5

10 Development Board User s Guide Each switch has two positions: Connect or Bypass. The Connect position places the selected device into the JTAG chain; the Bypass position removes the device from the JTAG chain. Although all three devices can be connected to the JTAG configuration chain during programming, Altera recommends connecting only those devices being programmed. APEX 20KE device SW7 SW6 SW5 Configuration controller SW10 SW8 SW9 PMC Connect Bypass Slide switch to one of these positions 1 The configuration controller should not be reprogrammed. Changing the configuration controller program will alter the functionality of the Nios Development Board and possibly make it inoperable. Power Supply A modular plug-in power supply accompanies the Nios Development Board. This 9 volt power supply plugs into connector J1 (negativecentered) and supplies the input power for the on-board power management. The on-board power management produces the following three voltages: 3.3 volts Used by the majority of the components on the board, including all APEX IO banks. 1.8 volts Used as the core voltage for the APEX EP20K200E device. 6

11 5 volts Provided for optional use with the 5V-tolerant Altera daughter card connectors. Four ground points (TP1 TP4) provide a ground plane reference. Serial Port The Nios Development Board contains one serial port connector (J3) for communications between the APEX EP20K200E and an external device. The serial port connects via a DB-9 type connector through an RS-232 transceiver (U13). The board has an unstuffed 6-pin header at location JP14 to assist in debugging the serial signals. Switches and Other Features The Nios Development Board contains several switches and LEDs. The Reset switch and switches SW8, SW9 and SW10 have fixed (unchangeable) function; the function of the Power LED (LED7) and LED3 are also fixed. The Clear switch is activated as part of the Nios Development Board's default program. However, the other switches and LEDS may be used by the developer to provide various inputs or for simulating real-world interaction in an embedded system. Two types of clock signals are also provided. The purpose and functionality of these assets are described below: SW1: User-Specific Functions SW1 is a dual in-line package (DIP) of eight single-pole switches connected to the APEX EP20K200E device I/O pins that can be used for user-specific functions. The signals are logic 1 when open. 7

12 Development Board User s Guide SW2: Reset Function Reset clears the APEX EP20K200E device and causes the configuration controller to load a new configuration from the on-board flash memory. The new configuration may be either the factory default (stored beginning at address 0x1C0000) or a user defined configuration (stored beginning at address 0x180000). SW3: Clear Function The clear function is defined by the factory default configuration (JP2 open) as a CPU reset for the Nios embedded processor. A specific user configuration (JP2 shorted) may define a function to this switch. SW4 - SW7: User-Specific Functions These four push-button switches, connected to APEX I/O pins, are available for user-specific functions. The signals are logic 0 when pressed. LEDs The board includes two user LEDs and two special purpose LEDs. LED1 and LED2 are available as user-defined LEDs, and are connected to APEX EP20K200E device I/O pins. LED7 indicates the presence of 3.3 volt power on the board. LED3 indicates that the configuration controller has finished configuring the APEX EP20K200E device. 1 LED3 does not indicate successful configuration of the APEX EP20K200E device, but only that the configuration controller has finished sending data to the APEX device. 8

13 Clocks The Nios Development Board has the following two types of clock networks: The first clock network is generated by the oscillator (Y1), and driven to components by the clock distribution chip (U5). Y1 is a MHz oscillator. The oscillator frequency is driven to the APEX CLK2 (pin L6), the two prototype daughter cards, and the configuration controller. The second type of clock network carries a signal produced by the phase-locked loop circuitry on the APEX EP20K200E device. The user has the option of producing a clock with the PLL circuit by use of the altcklock megafunction in the Quartus software, which may be driven off-chip via pin P5 (CLKLK_OUT1p). This signal is fed to the clock distribution chip (U5), and fed to both Altera daughter cards, the SODIMM connector, and the PMC connectors. The oscillator may be replaced at the user s discretion, but the configuration controller design may fail to successfully configure the APEX EP20K200E device if the clock frequency is greater than 66.8MHz. 9

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