Data Sheet. VL210 USB 3.0 Hub Controller 1 Port USB3.0 and 3 Ports USB2.0. March 31, 2014 Revision VIA Labs, Inc.

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Data Sheet VL210 USB 3.0 Hub Controller 1 Port USB3.0 and 3 Ports USB2.0 March 31, 2014 Revision 0.80 VIA Labs, Inc. www.via-labs.

1 Data Sheet VL210 USB 3.0 Hub Controller 1 Port USB3.0 and 3 Ports USB2.0 March 31, 2014 Revision 0.80 VIA Labs, Inc. 7F, 529-1, Zhongzheng Rd., Xindian District, New Taipei City 231 Taiwan Tel: (886-2) Fax: (886-2) sales@via-labs.com.tw

2 Revision History Revision No. Draft Date History Initial 0.56 Dec Preliminary Engineering Draft Release. TS 0.60 Jan Updated Feature List to reflect ACA Charging Support TS 0.80 Mar Correct the typo. Correct the TID. AY - 2 -

3 Contents Product Feature VL210 System Overview Rapid Charging over USB in Detail Pinout Pin List Pin Descriptions Signal Type Definition USB 3.0 Interface USB 2.0 Interface Analog Command Block Power and Ground Test Pin Side Band signal and Miscellaneous Electrical Specification Timing Requirements for SPI Flash General Reflow Profile Guidelines Package Mechanical Specifications (QFN-48) Package Top Side Marking & Ordering Information List of Figures Figure 1 VL210 Block Diagram Figure 2 VL210-Q4 QFN-48 Package Pin Diagram Figure 3 - Illustration of SPI Flash Interface Timing (1) Figure 4 - Illustration of SPI Flash Interface Timing (2) Figure 5 - Reflow Figure 6 - Mechanical Specification: QFN-48 6x6x0.85 mm Package Figure 7 - Package Top Side Marking List of Tables Table 1 VL210 QFN-48 Package Pin List

4 Product Feature VL210: Super-Speed USB Hub Controller 1 Port USB3.0 and 3 Ports USB2.0 USB 3.0 Compliant Compliant to Universal Serial Bus 3.0 Specification Rev 1.0, including Hub errata Compliant to Universal Serial Bus Specification Revision 2.0 Supports simultaneous Super-speed(SS), high-speed (HS), full-speed (FS) traffic, and low-speed (LS) traffic Four down-stream ports, one up-stream port In-house USB PHY employs advanced CMOS process for low power consumption Supports USB Low-Power States such as Ux states and Selective Suspend Full Sideband Signal Support Supports either individual mode or gang mode operation for power enable and over current detection on down-stream ports Supports LED status indicators with automatic or manual control via GPIO per down-stream port 2x GPIO, reserved for special functions Comprehensive USB Battery Charging Support Supports USB Battery Charging Specification v1.2 (SDP, CDP, DCP) Adds Support for Vendor Specific Charging Modes eg. Apple, RIM, etc. Supports YD/T Supports Sleep Charging (DCP + Apple Mode) Supports charging across all down-stream ports, depending on configuration Supports charging on upstream port to USB Host via USB Battery Charging ACA Configuration Physical QFN 48L green package (6x6x0.85 mm) Certification (TBD) Earned USB 2.0 USB-IF certification Earned USB 3.0 USB-IF certification TID# Passed Windows HCK Logo for Windows 8, RT Applications Standalone USB hub. Desktop/Notebook motherboard on-board hub Desktop front panel hub Notebook/Ultrabook Docking Station / Port Replicator USB hub compound device with keyboard, mouse, display, etc. Platform and Operating System Support Standalone USB hub Desktop/Notebook motherboard on-board hub Desktop front panel hub Notebook/Ultrabook Docking Station / Port Replicator USB hub compound device with keyboard, mouse, display, etc Misc Optimized for Low Power consumption Integrated 5V to 3.3V LDO and 5V to 1.2V Switching Regulators 3.3 V and 1.2 V power supply PLL embedded with external 25MHz crystal Support external SPI flash for firmware upgrade - 4 -

5 VL210 System Overview VIA Lab s VL210 is a 4 th generation advanced USB 3.0 Hub controller featuring a simplified port configuration. VL210 features four downstream ports: a single USB 3.0 and three USB 2.0 ports, each with comprehensive USB Charging without the need for external charger ICs. The VL210 employs an advanced CMOS process for greatly reduced power consumption and fully supports USB power management and low-power states. The custom in-house USB PHY gives VL210 excellent signal integrity characteristics under a variety of channel conditions and now supports improved USB EMI profile support including the new 2.4GHz Radio Friendly mode. VL210 features a highly flexible firmware architecture, providing a framework for custom functions as well as advanced feature support in addition to in-field updates. VL210 hub devices work under Windows, Mac OS X, and various Linux kernels without additional drivers. Since USB 3.0 hubs do not require additional drivers, VL210 is also compatible with non-x86 devices and platforms that support USB hub functions such as smart phones, tablets, and set-top boxes. It is well suited for all USB hub applications such as stand-alone USB hubs, Notebook/Ultrabook docking stations/port-replicators, desktop PC front panel, 2-in-1 convertible Tablets, and USB hub compound devices. With well-planned pinout and a high level of integration, VL210 based devices enjoy easy layout and simplified BOM. Full sideband signal pins are available for showing power enable, over current, GPIO, and LED status control. The SPI interface supports external EEPROM/Flash ROM which can be updated over USB. VL210 is available in QFN 48L package (6x6x0.85 mm). Figure 1 VL210 Block Diagram - 5 -

6 Rapid Charging over USB in Detail 3 Concepts of Rapid Charging over USB: (1) Rapid Charging over USB enables charging of devices at rates in excess of baseline USB standards. The current limit of USB 2.0 is 500mA for configured devices, and the current limit of USB 3.0 is 900mA for configured devices. Depending on the device, Rapid Charging implementations typically feature current limits between 1000mA to 2000mA. (2) It is the Host/Hub s responsibility to advertise Rapid Charging capabilities, and it is the Device s responsibility to recognize and determine the Rapid Charging capabilities of the Host/Hub port it is connected to. Since Rapid Charging over USB allows charging at rates in excess of USB spec, this detection mechanism is necessary to ensure safe and reliable operation, and can prevent situations where a device requests more current than what a host/hub port can supply. Also, this implies that Rapid Charging will only occur when both Host/Hub and Device supports it. (3) The rate at which a device charges is dependant upon the device. This means that the device must determine the host/hub port s capabilities to determine which charging mode to use. Also, the rate at which a device charges can vary depending on the status of the device. For example, some devices only charge at their maximum rate when the battery is nearly depleted. When the battery is nearly full, they may switch to a trickle-charge mode. The Host/Hub rapid-charging port has no control over this behavior. Supported USB Charging Modes SDP Standard Downstream Port This is a typical USB 2.0 or USB 3.0 port and does not explicitly support Rapid USB Charging. SDP is constrained to the current limits as defined in the USB 2.0 or USB 3.0 spec which are 500mA and 900mA respectively. While the actual current limit is enforced by the polyfuse or power-switch providing current-limiting functionality for the downstream port, most USB devices will not draw more than 500mA or 900mA under USB 2.0 or USB 3.0 modes. CDP Charging Downstream Port CDP is defined in the USB Battery Charging Specification 1.2 and enables devices that are able to correctly recognize CDP to simultaneously function as a USB device while drawing up to 1.5A for Rapid Charging when connected to the downstream port of a USB Host or Hub that advertises CDP capability. DCP Dedicated Charging Port DCP is defined in the USB Battery Charging Specification 1.2 and has been in use on an unofficial basis prior to the official USB Battery Charging Specification. DCP is a dedicated charging mode, so when a device is charging under DCP, regular USB operations such as data transfer to the device are not supported. Special Modes Various vendors such as Apple, RIM, Motorola, etc. may employ different detection mechanisms compared to other USB devices and thus, may enter Rapid Charging under the previously mentioned charging modes. VL811+ supports an auto detection mechanism that provides charging for the majority of devices

7 Pinout Figure 2 VL210-Q4 QFN-48 Package Pin Diagram - 7 -

8 Pin List Pin Pin Name Pin Pin Name 1 USBOC2#/SMCLK 25 SSTX0-2 USBPE2 26 SSTX0+ 3 HSD2+ 27 SSRX0-4 HSD2-28 SSRX0+ 5 USBPE3 29 SSXO 6 USBOC3# 30 SSXI 7 HSD3+ 31 USBPE0 8 HSD3-32 ACAID/USBOC0# 9 HSD4+ 33 USBLED1/SPISI 10 HSD4-34 USBLED2/SPISCLK 11 REXT 35 USBLED3/SPISO 12 VCC12O(LX) 36 USBLED4/SPICS# 13 VCC5I 37 SSTX1+ 14 VCC33O 38 SSTX1-15 USBPE4 39 SSRX1+ 16 USBOC4# 40 SSRX1-17 TESTEN 41 HSD1+ 18 RESET# 42 HSD1-19 VBUSDET 43 VCC12I 20 EXTPWRON 44 VCC33I 21 VCC33I 45 GPIO1 22 VCC12I 46 GPIO2 23 HSD0-47 USBPE1 24 HSD0+ 48 USBOC1#/SMDAT Table 1 VL210 QFN-48 Package Pin List - 8 -

9 Pin Descriptions Signal Type Definition Name Type Signal Description Input I A logic input-only signal Output O A logic output only signal Input/Output I/O A logic bi-directional signal Power PWR A power pin Ground GND A ground pin USB 3.0 Interface Pin Name Pin # I/O Signal Description SSTX0+ 26 USB 3.0 UP Port Differential Transmit Data + SSTX0-25 USB 3.0 UP Port Differential Transmit Data - SSRX0+ 28 USB 3.0 UP Port Differential Receive Data + SSRX0-27 USB 3.0 UP Port Differential Receive Data - SSTX1+ 37 USB 3.0 DP1 Port Differential Transmit Data + SSTX1-38 USB 3.0 DP1 Port Differential Transmit Data - SSRX1+ 39 USB 3.0 DP1 Port Differential Receive Data + SSRX1-40 USB 3.0 DP1 Port Differential Receive Data - USB 2.0 Interface Pin Name Pin # I/O Signal Description HSD0+ 24 USB 2.0 UP Bus Data Plus (D+) HSD0-23 USB 2.0 UP Bus Data Minus (D ) HSD1+ 41 USB 2.0 DP1 Bus Data Plus (D+) HSD1-42 USB 2.0 DP1 Bus Data Minus (D ) HSD2+ 3 USB 2.0 DP2 Bus Data Plus (D+) HSD2-4 USB 2.0 DP2 Bus Data Minus (D ) HSD3+ 7 USB 2.0 DP3 Bus Data Plus (D+) HSD3-8 USB 2.0 DP3 Bus Data Minus (D ) HSD4+ 9 USB 2.0 DP4 Bus Data Plus (D+) HSD4-10 USB 2.0 DP4 Bus Data Minus (D ) - 9 -

10 Analog Command Block Pin Name Pin # I/O Signal Description SSXI 30 25M crystal input SSXO 29 25M crystal output REXT 11 Connect to reference resistor Power and Ground Pin Name Pin # I/O Signal Description VCC12I 22 PWR 1.2V Core power VCC33I 21,44 PWR 3.3V Core power VCC5I 13 PWR 5-3.3V LDO Input, 5-1.2V Regulator Input VCC33O 14 PWR 3.3V LDO Output VCC12I 43 PWR 5-1.2V Feedback, 1.2V Input VCC12O(LX) 12 PWR 5-1.2V Regulator Output Test Pin Pin Name Pin # I/O Signal Description TESTEN 17 I Test Mode Enable Do not connect for normal operation. Internal pull down. Low: Normal mode. High: Test mode

11 Side Band signal and Miscellaneous Pin Name Pin # I/O Signal Description USBLED1/SPISI 33 O USBLED2/SPICLK 34 O USBLED3/SPISO 35 O USBLED4/SPICS# 36 O USBPE1 47 O USBPE2 2 O USBPE3 5 O USBPE4 15 O ACAID/USBOC0# 32 I/O USBOC1#/SMDAT 48 I/O USBOC2#/SMCLK 1 I/O USBOC3# 6 I USBOC4# 16 I DP1 LED Indicator and SPISI share pin. For LED, output high when active and external 100Kohm pull low required. DP2 LED Indicator / SPISCLK share pin. For LED, output high when active and external 100Kohm pull low required. DP3 LED Indicator and SPISO share pin. For LED, output high when active and external 100Kohm pull low required. DP4 LED Indicator / SPICS# share pin. For LED, output high when active and external 100Kohm pull low required. DP1 Power Enable. Low: Port Power On. High: Port Power Off. DP2 Power Enable. Low: Port Power On. High: Port Power Off. DP3 Power Enable. Low: Port Power On. High: Port Power Off. DP3 Power Enable. Low: Port Power On. High: Port Power Off. UP Over Current Detect Low: Port Over Current High: Port Power Normal DP1 Over Current Detect Low: Port Over Current High: Port Power Normal SMBus data for debug only. It is not a standard SMBus interface. Open Drain DP2 Over Current Detect Low: Port Over Current High: Port Power Normal SMBus clock for debug only. It is not a standard SMBus interface. Open Drain DP3 Over Current Detect Low: Port Over Current High: Port Power Normal DP4 Over Current Detect Low: Port Over Current High: Port Power Normal EXTPWRON 20 I Upstream Port VBUS Detection for Upstream port plug-in RESET# 18 I System Reset Low: Reset High: Normal Operation VBUSDET 19 I 5V USB VBus Presence Detect GPIO1 45 I/O GPIO Pin reserved for special function GPIO2 46 I/O GPIO Pin reserved for special function

12 Electrical Specification Absolute Maximum Rating Symbol Parameter Min Max Unit Note T STG Storage Temperature C V V Power Supply Voltage V V V Input Voltage V V IN Input voltage at I/O pins -0.5 ( 3.63) and ( V ) V ESD Electrostatic Discharge V θ jc θ ja Thermal resistance between junction and case Thermal resistance between junction and ambient P D Max Power Dissipation For 4-layer PCB: 9.1 For 2-layer PCB: 11.3 For 4-layer PCB: 21.8 For 2-layer PCB: V C/W C/W W Human Body Model 2L & 4L PCB definitions follow JESD51-7 Q8P 4-Port Q4S 2-Port Note: Stress above conditions may cause permanent damage to the device. Functional operation of this device should be restricted to the conditions described. Note: About thermal factors, T a is the concerned ambient temperature, and θ ca = θ ja - θ jc T J = θ ja * P D + T a T c = θ ca * P D + T a Operating Conditions Symbol Parameter Min Max Unit Note T A Ambient Temperature 0 70 C T j Junction Temperature C V V Power Supply Voltage V V V Input Voltage V 1.2 Nominal V IL Input Low Voltage 0.8 V V IH Input High Voltage 2.0 V V OL Output Low Voltage 0.4 V I OL =4mA V OH Output High Voltage 2.4 V I OH =4mA I IL Input Leakage Current +/-10 µa 0<V i <V 33 I OZ Tristate Leakage Current +/-20 µa 0<V o <V

13 Timing Requirements for SPI Flash SPI flash ROM is used to store the FW data for VL210. Timing guidelines are provided to assist in selection of appropriate and compatible SPI flash. To ensure SPI flash suitability, not only should the timing requirements conform to the provided guidelines, but actual testing with VL811+ should also be done. Symbol Parameters Condition Value Unit f CT Clock Frequency for fast read mode(*) Max value must larger than 15 MHz f C Clock Frequency for read mode Max value must larger than 15 MHz t RI Input Rise time Max value must larger than 5 ns t FI Input Fall time Max value must larger than 5 ns t CKH SCK High Time Min value must smaller than 20 ns t CKL SCK Low Time Min value must smaller than 20 ns t CEH CE# High Time Min value must smaller than 100 ns t CS CE# Setup Time Min value must smaller than 20 ns t CH CE# Holde Time Min value must smaller than 100 ns t DS Data In Setup Tiime Min value must smaller than 20 ns t DH Data In Hold Time Min value must smaller than 20 ns t HS Hold Setup Time Not Utilized t HD Hold Time Not Utilized t V Output Valid Max value must smaller than 20 ns t OH Output Hold Time Normal Mode Not Utilized t LZ Hold to Output Low Z Not Utilized t HZ Hold to Output High Z Not Utilized t DIS Output Disable Time Not Utilized t EC Erase Time Max value must smaller than 100 ms t PP Page Program Time Max value must smaller than 100 ms t VCS Vcc Setup Time Min value must smaller than 1 ms t w Write Status Register Time (Flash bit) Max value must smaller than 100 ms *Fast read mode must be supported

14 Figure 3 - Illustration of SPI Flash Interface Timing (1) Figure 4 - Illustration of SPI Flash Interface Timing (2)

15 General Reflow Profile Guidelines Figure 5 - Reflow

16 Package Mechanical Specifications (QFN-48) Maximum Temperature for IR Reflow Parameter Value Unit Maximum Temperature Tp 255 C Max Time within 5 C of Tp 30 seconds Figure 6 - Mechanical Specification: QFN-48 6x6x0.85 mm Package

17 Package Top Side Marking & Ordering Information Figure 7 - Package Top Side Marking Ordering Information Description Package Type VL210-Q4 1SS 3HS Hub: 1x USB 3.0 & 3x USB 2.0 QFN48 6x6 mm

18 VIA Labs, Inc. 7F, 529-1, Zhongzheng Rd., Xindian District, New Taipei City 231 Taiwan Tel: (886-2) Fax: (886-2) Copyright 2014 VIA Labs, Inc. All Rights Reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Labs, Inc. The material in this document is for information only and is subject to change without notice. VIA Labs, Inc. reserves the right to make changes in the product design without reservation and without notice to its users. All trademarks are the properties of their respective owners. No license is granted, implied or otherwise, under any patent or patent rights of VIA Labs, Inc. VIA Labs, Inc. makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable as of the publication date of this document. However, VIA Labs, Inc. assumes no responsibility for any errors in this document. Furthermore, VIA Labs, Inc. assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change

Data Sheet. VL812 USB 3.0 Hub Controller. VL812 USB 3.0 Hub Controller. April 24, 2012 Revision VIA Labs, Inc.

Data Sheet. VL812 USB 3.0 Hub Controller. VL812 USB 3.0 Hub Controller. April 24, 2012 Revision VIA Labs, Inc. Data Sheet VL812 USB 3.0 Hub Controller April 24, 2012 Revision 0.86 VIA Labs, Inc. www.via-labs.com 7F, 529-1, Zhongzheng Rd., Xindian District, New Taipei City 231 Taiwan Tel: (886-2) 2218-1838 Fax: