Stereo PDM-to-I 2 S or TDM Conversion IC ADAU7002
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1 Data Sheet FEATURES 64 decimation of a stereo pulse density modulation (PDM) bit stream to pulse code modulation (PCM) audio data Slave I 2 S or time division multiplexed (TDM) output interface Configurable TDM slots I/O supply operation: 1.62 V to 3.6 V 64 output sample rate PDM clock 64 /128 /192 /256 /384 /512 output sample rate Automatic ratio detection Output sample rate: 4 khz to 96 khz Automatic PDM CLK drive at 64 the sample rate Automatic power down with removal 0.67 ma operating current at 48 khz and 1.8 V IOVDD supply Shutdown current: <1 µa 8-ball, 1.56 mm 0.76 mm, 0.4 mm pitch WLCSP Power-on reset Stereo PDM-to-I 2 S or TDM Conversion IC GENERAL DESCRIPTION The converts a stereo PDM bit stream into a PCM output. The source for the PDM data can be two microphones or other PDM sources. The PCM audio data is output on a serial audio interface port in either I 2 S or TDM format. The is specified over the commercial temperature range ( 40 C to +85 C). It is available in a halide-free, 8-ball, 1.56 mm 0.76 mm, wafer level chip scale package (WLCSP). APPLICATIONS Mobile computing Portable electronics Consumer electronics FUNCTIONAL BLOCK DIAGRAM 1.62V TO 3.6V CONFIG GND IOVDD PDM_CLK PDM_DAT PDM INPUT PORT DIGITAL DECIMATION FILTERING I 2 S OUTPUT PORT Figure Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support
2 TABLE OF CONTENTS Features... 1 Applications... 1 General Description... 1 Functional Block Diagram... 1 Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 4 Thermal Resistance... 4 ESD Caution... 4 Data Sheet Pin Configuration and Function Descriptions...5 Typical Performance Characteristics...6 Typical Application Circuit...8 Applications Information...9 Overview...9 Clocking...9 Serial Audio Output Interface...9 Outline Dimensions Ordering Guide REVISION HISTORY 7/13 Rev. 0 to Rev. A Changes to Supply Current Test Conditions/Comments... 3 Changes to Figure Added Figure 6; Renumbered Sequentially... 6 Changes to Figure 14 and Figure Changes to Figure 16, Figure 17, and Figure Changes to Figure 19, Figure, and Figure /13 Revision 0: Initial Version Rev. A Page 2 of 16
3 Data Sheet SPECIFICATIONS IOVDD = 1.8 V, TA = 25 C, = MHz, output = 48 khz, I 2 S format, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL INPUT/OUTPUT High Level Input Voltage (VIH) 0.7 IOVDD V Low Level Input Voltage (VIL) 0.3 IOVDD V Input Leakage, High (IIH) and pins 1 µa Input Leakage, Low (IIL) and pins 1 µa Input Capacitance 5 pf 4.5 ma PDM_CLK 9 ma PERFORMANCE Dynamic Range Hz to khz, 60 db input With A-Weighted Filter (RMS) 110 db Signal-to-Noise-Ratio A-weighted, fourth-order input 110 db Decimation Ratio 64 Frequency Response DC to 0.45 output fs db Stop Band fs Stop-Band Attenuation 60 db Group Delay 0.02 fs input signal 3.31 cycles Gain PDM to PCM 0 db Start-Up Time 48 cycles Bit Width Internal and output Bits Interchannel Phase 0 Degrees CLOCKING Output Sampling Rate fs pulse rate khz Frequency f MHz POWER SUPPLIES Supply Voltage Range IOVDD V Supply Current IOVDD = 1.8 V 0.67 ma IOVDD = 3.3 V 1.33 ma IOVDD = 1.8 V, 16 khz output 0.21 ma IOVDD = 3.3 V, 16 khz output 0.41 ma Shutdown Current IOVDDSD, no input clocks 1 µa Rev. A Page 3 of 16
4 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25 C, unless otherwise noted. Table 2. Parameter Rating IOVDD Supply Voltage 3.6 V Input Voltage 3.6 V ESD Susceptibility 4 kv Storage Temperature Range 65 C to +150 C Operating Temperature Range 40 C to +85 C Junction Temperature Range 65 C to +165 C Lead Temperature (Soldering, 60 sec) 300 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Data Sheet θja (junction to air) is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. θja is determined according to JESD51-9 on a 4-layer printed circuit board (PCB) with natural convection cooling. Table 3. Thermal Resistance Package Type θja Unit 8-ball, 1.56 mm 0.76 mm WLCSP 90 C/W ESD CAUTION Rev. A Page 4 of 16
5 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER 1 2 A PDM_ DAT PDM_ CLK B C GND D IOVDD CONFIG TOP VIEW (BALL SIDE DOWN) Figure 2. Pin Configuration (Top Side View) Table 4. Pin Function Descriptions Pin No. Mnemonic Type Description A1 PDM_DAT Input PDM Data Input A2 PDM_CLK Output PDM Clock Output B1 Output Serial Data Output for I 2 S/TDM B2 Input Bit Clock for I 2 S/TDM C1 GND Ground Ground C2 Input Left/Right Clock for I 2 S/Frame Sync for TDM D1 IOVDD Supply Input/Output and Digital Supply D2 CONFIG Input Configuration Pin Rev. A Page 5 of 16
6 TYPICAL PERFORMANCE CHARACTERISTICS LEVEL (dbfs) CH1 CH k 10k k FREQUENCY (Hz) Figure 3. FFT, fs = 48 khz, 60 dbfs Input GROUP DELAY (µs) Figure 6. Group Delay vs. Frequency, fs = 48 khz Data Sheet k 10k 100k FREQUENCY (Hz) LEVEL (dbfs) THD + N (dbfs) NORMALIZED FREQUENCY (RELATIVE TO f S ) (Hz) 8 Figure 4. Frequency Response NORMALIZED FREQUENCY (RELATIVE TO f S ) (Hz) Figure 7. Total Harmonic Distortion + Noise (THD + N) vs. Normalized Frequency (Relative to fs) GROUP DELAY ( CYCLES) THD + N LEVEL (dbfs) NORMALIZED FREQUENCY (RELATIVE TO f S ) (Hz) Figure 5. Group Delay vs. Normalized Frequency (Relative to fs) GENERATOR LEVEL (dbfs) Figure 8. THD + N Level vs. Generator Level Rev. A Page 6 of 16
7 Data Sheet SUPPLY CURRENT (ma) SUPPLY VOLTAGE (V) Figure 9. Supply Current vs. Supply Voltage MAGNITUDE (db) FREQUENCY (MHz) Figure 10. Out-of-Band Frequency Response (48 khz Output) Rev. A Page 7 of 16
8 Data Sheet TYPICAL APPLICATION CIRCUIT IOVDD 0.1µF IOVDD PDM_CLK PDM_CLK PDM_DAT PDM_DAT CONFIG CONFIG GND OPTIONAL PULL-DOWN RESISTOR Figure 11. Typical Application Circuit Rev. A Page 8 of 16
9 Data Sheet APPLICATIONS INFORMATION OVERVIEW The provides stereo decimation from a 1-bit PDM source to a -bit PCM audio. The downsampling ratio is fixed at 64. The -bit downsampled PCM audio is output via standard I 2 S or TDM formats. The input source for the can be any device that has a PDM output, such as a digital microphone like the ADMP521. The output pins of these microphones can connect directly to the input pins of the. CLOCKING The requires a rate that is a minimum of 64 the sample rate. rates of 128, 192, 256, 384, and 512 the rate are also supported. The automatically detects the ratio between and and generates a PDM clock output at 64 the rate. The minimum sample rate is 4 khz, and the maximum is 96 khz, which correspond to a PDM clock range of 256 khz to MHz. Internally, all processing is done at the PDM_CLK rate. When is removed, the powers down automatically. When is not present, the PDM_CLK output stops. Table 5. PDM Timing Parameters Parameter tmin tmax Unit Data Setup Time, tsetup 10 ns Data Hold Time, thold 7 ns PDM data is latched on both edges of the clock. PDM_CLK t SETUP PDM_DAT R L R L Figure 12. PDM Timing Diagram t HOLD SERIAL AUDIO OUTPUT INTERFACE The supports I 2 S and TDM serial output formats. Format selection and TDM slot placement is set with the CONFIG pin. The pin is in tristate mode, except when the port is driving serial data based on the CONFIG pin configuration Table 6. TDM Slot Selection Device Setting I 2 S Format TDM Slot 1 to Slot 2 Used/Driven, 32-Bit Slots TDM Slot 3 to Slot 4 Used/Driven, 32-Bit Slots TDM Slot 5 to Slot 6 Used/Driven, 32-Bit Slots TDM Slot 7 to Slot 8 Used/Driven, 32-Bit Slots CONFIG Pin Configuration Tie to IOVDD Tie to GND Open Tie to IOVDD through a 47 kω resistor Tie to GND through a 47 kω resistor Rev. A Page 9 of 16
10 Data Sheet Serial Port Timing t BIH t BIL t LIS t LIH TDM MODE t SODM MSB MSB 1 I 2 S JUSTIFIED MODE t SODM MSB Figure 13. Serial Port Timing Diagram Table 7. I 2 S/TDM Timing Parameters Parameter Symbol tmin tmax Unit Pulse Width High tbih 10 ns Pulse Width Low tbil 10 ns Setup Time tlis 10 ns Hold Time tlih 10 ns Time from Falling tsodm 10 ns I 2 S LEFT CHANNEL TRISTATE I 2 S RIGHT CHANNEL TRISTATE s Figure 14. I 2 S, CONFIG Pin Tied to IOVDD LEFT RIGHT TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE s SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 Figure 15. TDM8 Channel 1 and Channel 2, CONFIG Pin Tied to GND Rev. A Page 10 of 16
11 Data Sheet TRISTATE TRISTATE LEFT RIGHT TRISTATE TRISTATE TRISTATE TRISTATE SLOT 1 s SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 Figure 16. TDM8 Channel 3 and Channel 4, CONFIG Pin Open TRISTATE TRISTATE TRISTATE TRISTATE LEFT RIGHT TRISTATE TRISTATE SLOT 1 s SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 Figure 17. TDM8 Channel 5 to Channel 6, CONFIG Pin Tied to IOVDD Through a 47 kω Resistor TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE LEFT RIGHT SLOT 1 s SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 Figure 18. TDM8 Channel 7 and Channel 8, CONFIG Pin Tied to GND Through a 47 kω Resistor Rev. A Page 11 of 16
12 Data Sheet LEFT RIGHT TRISTATE TRISTATE s SLOT 1 SLOT 2 SLOT 3 SLOT 4 Figure 19. TDM4 Channel 1 and Channel 2, CONFIG Pin Tied to IOVDD TRISTATE TRISTATE LEFT RIGHT s SLOT 1 SLOT 2 SLOT 3 SLOT 4 Figure. TDM4 Channel 3 and Channel 4, CONFIG Pin Open LEFT s RIGHT SLOT 1 SLOT 2 Figure 21. TDM2 Channel 1 and Channel 2, CONFIG Pin Tied to IOVDD Rev. A Page 12 of 16
13 Data Sheet OUTLINE DIMENSIONS BOTTOM VIEW (BALL SIDE UP) 2 1 ORIENTATION IDENTIFIER A BALL A1 IDENTIFIER REF B C TOP VIEW (BALL SIDE DOWN) 0.40 BSC 0.40 BSC D SIDE VIEW COPLANARITY 0.05 SEATING PLANE Figure Ball Wafer Level Chip Scale Package [WLCSP] (CB-8-6) Dimensions shown in millimeters A ORDERING GUIDE Model 1 Temperature Range Package Description Package Option Branding ACBZ-R7 40 C to +85 C 8-Ball Wafer Level Chip Scale Package [WLCSP], 7 Tape and Reel CB-8-6 BE ACBZ-RL 40 C to +85 C 8-Ball Wafer Level Chip Scale Package [WLCSP], 13 Tape and Reel CB-8-6 BE EVAL-Z Evaluation Board 1 Z = RoHS Compliant Part. Rev. A Page 13 of 16
14 Data Sheet NOTES Rev. A Page 14 of 16
15 Data Sheet NOTES Rev. A Page 15 of 16
16 Data Sheet NOTES 13 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /13(A) Rev. A Page 16 of 16
17 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: EVAL-Z ACBZ-R7 ACBZ-RL
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