PCI Interrupts for x86 Machines under FreeBSD
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1 PCI Interrupts for x86 Machines under FreeBSD May 18, 2007 John Baldwin
2 Introduction Hardware for PCI INTx interrupts x86 CPU interrupts PCI INTx signals x86 interrupt controllers Interrupt Routing PCI-PCI bridge swizzle Tables: $PIR, MP Table, ACPI _PRT Message Signaled Interrupts 2
3 x86 CPU Interrupts OS provides array of handlers called Interrupt Descriptor Table (IDT) Each interrupt contains vector which indexes table Vectors 0-31 reserved for Faults/Exceptions Vectors available for device interrupts, IPIs, etc. 3
4 PCI INTx PCI slots have 4 interrupts, INTB#, INTC#, INTD# PCI functions use 1 interrupt from parent slot Function Function Function Function INTB# INTC# PCI Slot INTD# 4
5 x86 Interrupt Controllers 8259A PICs (PC-AT) Programmable Interrupt Router APICs 5
6 8259A & PIR PCI Slot 0 PIR To CPU PCI Slot 1 PCI Slot 2 PCI Slot 3 LNKA LNKB LNKC LNKD O0 O1 O2 O3 Printer Floppy COM1 COM2 Keyboard ISA Timer I7 I6 I5 I4 I3 I2 I1 I0 INTR Master 8259A PCI Slot 4 PCI Slot 5 Sec IDE Pri IDE FPU Mouse RT Clock I7 I6 I5 I4 I3 I2 I1 I0 INTR Slave 8259A 6
7 I/O APIC PCI Slot 0 PCI Slot 1 I23 I22 I21 I20 I19 I18 I17 I16 PCI Slot 2 PCI Slot 3 PCI Slot 4 Sec IDE Pri IDE FPU Mouse RT Clock I15 I14 I13 I12 I11 I10 I9 I8 I/O APIC 7 PCI Slot 5 Printer Floppy COM1 COM2 Keyboard ISA Timer I7 I6 I5 I4 I3 I2 I1 I0
8 Interrupt Routing How everything is hooked together Maps PCI (bus, slot, pin) to input pin on 8259A or I/O APIC May have to detour through a PIR PCI-PCI bridge swizzle Various tables on x86 $PIR for 8259A & PIR MP Table for APIC 8 ACPI for both
9 PCI-PCI Bridge Swizzle Routes interrupts across bridge from downstream bus to upstream bus For PCI-PCI bridges in add-on cards new_pin = (child_slot + child_pin) % 4 Parent PCI Bus Slot A A B Bridge D C Slot A Slot A Child PCI Bus Slot A 9
10 $PIR Table 10 Entry Location Bus Device Pin Link IRQs 0 embedded 0 2 A 0x embedded 1 0 A 0x embedded 1 0 B 0x embedded 1 0 C 0x embedded 1 0 D 0x embedded 0 29 A 0x embedded 0 29 B 0x embedded 0 29 C 0x embedded 0 29 D 0x6b embedded 0 31 A 0x embedded 4 13 A 0x embedded 2 4 A 0x embedded 4 3 A 0x slot A 0x slot B 0x slot C 0x slot D 0x
11 MP Table I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# ExtINT active hi edge INT conforms conforms INT conforms conforms INT conforms conforms INT conforms conforms INT conforms conforms INT conforms conforms INT conforms conforms INT conforms conforms INT conforms conforms 0 2:A 8 16 INT conforms conforms 0 29:A 8 16 INT conforms conforms 0 29:B 8 19 INT conforms conforms 0 29:D 8 23 INT conforms conforms 0 31:A 8 18 INT conforms conforms 4 13:A 8 17 INT conforms conforms 4 3:A 8 20 INT conforms conforms 2 4:A 9 0 INT conforms conforms 3 7:A 10 2 INT conforms conforms 3 7:B 10 3 INT conforms conforms 3 7:C 10 0 INT conforms conforms 3 7:D
12 ACPI Global System Interrupts 0-15 are ISA IRQs 16+ are I/O APIC pins OS calls _PIC method to tell BIOS 8259A vs APIC Each PCI bus contains _PRT table Pins on Programmable Interrupt Router are Link Devices 12
13 Global System Interrupts Dual 8259As APIC
14 ACPI _PIC Method Scope (\) { Name (PICF, 0x00) Method (_PIC, 1, NotSerialized) { Store (Arg0, PICF) } } 14
15 ACPI _PRT Method Device (PXHB) {... Name (PIC3, Package (0x04) Method (_PRT, 0, NotSerialized) { { Package (0x04) If (LNot (PICF)) { { 0x0007FFFF, Store (PIC3, Local0) 0x00, } LNKC, Else 0x00 { }, Store (APC3, Local0)... } }) Name (APC3, Package (0x04) Return (Local0) { } Package (0x04) } { 0x0007FFFF, 0x00, 0x00, 0x42 },... }) 15
16 FreeBSD's PCI Interrupt Routing PCI bus asks parent bridge to route interrupt Requests propagate up device tree until answered Host-PCI Bridge Slot Bus 0 PCI-PCI Bridge Slot Bus 1 Slot 16
17 Mapping IRQs to IDT Vectors Interrupt routing routes PCI interrupt to interrupt controller pin (IRQ) FreeBSD uses GSI-like scheme to map interrupt controller pins to IRQs Allocate IDT vectors on-demand to IRQs 17
18 Message Signaled Interrupts Problems with INTx Interrupts Single interrupt per function Interrupt is a sideband signal Interrupt routing is a pain MSI Addresses These Problems Each function can have multiple messages Interrupt triggered via memory write Memory data contains IDT vector on x86 18
19 INTx Sideband Signals are Bad CPU RAM Host-PCI Bridge PIC PCI-PCI Bridge PCI Slot 19
20 FreeBSD's MSI Implementation PCI bus asks parent bridge for MSI IRQs x86 nexus driver creates MSI IRQs on the fly and assigns IDT vectors on-demand 20
21 Conclusion PCI INTx interrupts are messy Interrupt Routing can be painful, esp. on x86 MSI will hopefully be better PCI-express mandates it for PCI-express devices 21
22 Q&A Paper and slides are available online Questions? 22
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