1 PC Hardware Basics Microprocessors (A) PC Hardware Basics Fal 2004 Hadassah College Dr. Martin Land

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2 2 Basic Computer Ingredients Processor(s) and co-processors RAM main memory ROM initialization/start-up routines Peripherals: keyboard/mouse, display, mass storage, general I/O (printer, network, sound) Support circuitry: clocks, timers, counters, interrupt s, DMA s

3 3 Basic Computer Layout אפיק זיכרון Memory Bus זיכרון מטמון cache memory יהידת החישוב המרכזי Central Processing Unit (CPU) זיכרון ראשי Main Memory (RAM) אפיק קלט/פלט I/O Bus מתאם אפיק Bus Adapter בקר קלט/פלט I/O Controller בקר קלט/פלט I/O Controller בקר קלט/פלט I/O Controller Disk ממשק משתמש רשת תקשורת communications network

4 4 Chipsets Collection of related hardware devices Designed to work together efficiently Based on a common Architecture (design plan) Hardware technology (circuit type) Perform I/O and support functions

5 5 Bus-Oriented Mechanical Organization Used in large server systems Separate circuit board for each function CPU board Memory board I/O board Support board I/O Controller I/O Controller Central back-plane Usually passive bus Function boards plug into bus system Examples: mainframe computers I/O Controller Bus Adaptor Card Backplane Memory Card Memory Card CPU Card

6 6 Single Board Computer Organization Specially designed to fit onto one circuit board Smaller Designed for specific components Less flexible Example: PDAs, laptops, special purpose hardware (routers, s) CPU Subsystem I/O Subsystem Power Supply Single Board Computer Memory Subsystem I/O Controller I/O Controller I/O Controller

7 7 PC is a Compromise Processor, memory, and support hardware on a single board (motherboard) Smaller but less flexible Motherboard Peripherals plug into expansion bus More choice in choosing components for expansion CPU Subsystem I/O Subsystem Power Supply Memory Subsystem I/O Controller Expansion Slot I/O Controller Expansion Slot I/O Controller Expansion Slot I/O Controller Expansion Slot I/O Controller Expansion Slot

8 8 PC Bus Types Address Bus Proprietary Fast Includes data, address, control signals Local Bus (front end bus) Processor data and address lines In this case, between processor and L2 cache I/O bus For expansion addition of peripheral devices Published standard Permit OEM hardware to work with computer OEM = Original Equipment Manufacturer

9 9 Basic Functions of I/O Bus Power to devices Addressing and data transfer Timing signal to devices for data transfer Flow control data buffering Bus mastering and arbitration I/O Bus Power Address Data Clock Arbitration

10 10 Brief History of PC Bus Standards

11 11 IBM Proprietary Bus Designs PC bus IBM's original I/O bus Local bus 8-bit data transfer for 8088 AT bus (for 80286) Permits 16-bit data transfers Split 2-part connector Second connector for 8 new data bits First connector maintained compatibility with older cards

12 12 First Standardized Buses ISA Industry Standard Architecture IEEE standardization of the AT bus Standardizes support functions as well as I/O Permits a chipset to handle support and I/O in an integrated fashion EISA Enhanced Industry Standard Architecture Designed by consortium of clone OEMs Looking to block IBM market control Various improvements, such as 32-bit data bus

13 13 Local Bus Display Control Graphics bus connected directly to processor אפיק זיכרון Memory Bus זיכרון מטמון cache memory יהידת החישוב המרכזי Central Processing Unit (CPU) Local Bus Video Controller I/O Bus זיכרון ראשי Main Memory (RAM) אפיק קלט/פלט מתאם אפיק Bus Adapter בקר קלט/פלט I/O Controller בקר קלט/פלט I/O Controller בקר קלט/פלט I/O Controller Disk ממשק משתמש רשת תקשורת communications network

14 14 Display Control Requirements Screen memory is (units/screen) (bytes/unit) First PCs used text-oriented screen memory 25 rows of 80 monochrome characters Character represented by one ASCII byte Video memory is = 2000 Bytes/screen Graphics-oriented screen memory Consider 1024 by 768 pixel resolution at 24 bit color = 786,432 pixels/screen Each pixel requires 3-bytes (24 bits) for color Need = 2,359,296 Bytes/screen

15 15 VESA Local Bus Standard VESA - Video Electronics Standards Association Local bus connector in-line with EISA Double-connector made for screen card Special Driver required for local bus access

16 16 PCI Peripheral Component Interface Intel standard PCI Bridge replaces the I/O Adapter Controls all processor accesses PCI brings standardization to the memory bus

17 17 PCI Layout אפיק זיכרון Memory Bus Host PCI Bridge זיכרון ראשי Main Memory (RAM) זיכרון מטמון cache memory PCI bus יהידת החישוב המרכזי Central Processing Unit (CPU) ISA/EISA bus adapter PCI Graphics Adapter בקר קלט/פלט I/O Controller ממשק משתמש רשת תקשורת communications network Disk

18 18 Overview of ISA Bus

19 19 systems kernel ISA Block Diagram memory subsystem cache bus ROM RAM CPU X-bus ISA subsystem expansion bus keyboard mouse DMA interrupt Real Time clock and timers etc audio graphics network

20 20 ISA Subsystems Kernel: processor, bus control logic, electrical interface circuitry Memory Subsystem: RAM and ROM ISA Subsystem: Expansion (I/O) slots System functions X-bus Real time clock PIC Programmable interrupt DMA IRQ interrupt Keyboard Each device has its own I/O address

21 21 Address bus Data bus Control bus CPU I/O Structures Read/write (direction) Timing (clock) 8 MHz Interrupts

22 22 PC-AT Memory Map Upper Memory Above KB boot ROM F0000 to FFFFF 64 KB option ROM E0000 to EFFFF 128 KB device ROM C0000 to DFFFF 128 KB video memory A0000 to BFFFF 640 KB DOS program memory to 9FFFF Extended Memory Conventional Memory

23 23 PC-AT Data Path 16-bit data transfers Processor addresses 2 bytes with one low order address Lower data path I/O lines D0 to D7 Transfer bytes to/from even memory address Upper data path I/O lines D8 to D15 Transfer bytes to/from odd memory address I/O Bus Power Even Odd Address Clock Arbitration Data Data

24 Data Path Addresses 2 32 B = 4 GB 32-bit address: A31 A30 A3 A2 A1 A0 Processor addresses 4 bytes at one time Processor uses only 30 address lines A31 to A2 Generates address A31 A30 A3 A2 0 0 Access address is always a multiple of 4 = Memory management unit provides 4 bytes from addresses: A31 A30 A3 A2 0 0 A31 A30 A3 A2 0 1 A31 A30 A3 A2 1 0 A31 A30 A3 A2 1 1

25 25 Multiplexed DRAM Organization Use n/2 address lines for an n-bit memory chip Send address to chip in two transfer cycles Saves money in making chips Permits large inexpensive RAM Longer access time Example: 16 MB chip needs 24 address bits Multiplexing uses 12 address lines First, send Upper 12 bits of address Second, send Lower 12 bits of address

26 26 Internal Memory Chip Function RAS Row Address Strobe (first) CAS Column Address Strobe (second) RAS activates all columns in a row CAS chooses one column from selected row Chip response time spread over entire row RAS CAS bit Address = h RAS = 002 h CAS = 004 h

27 27 Interleaved Memory Arrange memory as an array of RAM chips Divide memory into banks (columns) Addressing one bank prepares next bank Chip response time distributed over banks Called burst mode read access A 1 A A n A n-1... A 2

28 28 RAM Chip Technologies Static RAM (SRAM) Several transistors per memory bit (flip-flop gates) Stable Fast and Expensive Dynamic RAM (DRAM) Capacitor and 1 transistor per memory bit Decays if not refreshed Slower and cheaper than DRAM Extended Data Out DRAM (EDO DRAM) Interleaved DRAM for faster data reads Synchronous DRAM (SDRAM) DRAM synchronized to system clock for faster reads RAMBUS (RDRAM) Fast proprietary type of SDRAM

29 29 Interrupts x86 has hardware/software interrupts 0 to 255 Software interrupts controlled by: Machine instruction INT int_number Fetches CS:IP vector from address int_number 4 Hardware interrupts controlled by: int_number on data bus signals D0 to D7 INTR (input control signal to processor) IRQ Interrupt Requests reserved for I/O hardware

30 30 Interrupt Controller Programmable Interrupt Controller (PIC) Pair of 8-input s in Master/Slave configuration Master controls Slave over Cascade Bus Master enables Slave outputs to processor data bus Receives 15 defined IRQs 8 interrupt inputs from Slave and 7 interrupt inputs from Master Translates IRQ into specific INTR, INT signals

31 31 Interrupt Controller Layout 8259 Master PIC IR 0 IR 1 IR 2 IR 3 IR 4 IR 5 IR 6 IR 7 INTR INT # INTR CPU D0 to D Slave PIC IR 0 IR 1 IR 2 IR 3 IR 4 IR 5 IR 6 IR 7 INTR INT # Cascade Bus

32 32 IRQ to CPU Hardware INT Table IRQ Line CPU Interrupt A (XT) cancelled (AT) 3 0B 4 0C 5 0D 6 0E 7 0F

33 33 DMA Direct Memory Access Peripheral device accesses memory directly No need for CPU to execute IN/OUT or MOV systems kernel instructions CPU can work cache with cache at the same bus ROM CPU time Used for large data transfers keyboard mouse DMA X-bus interrupt Real Time clock and timers etc memory subsystem ISA subsystem expansion bus audio graphics network RAM

34 34 DMA Operation CPU sets up DMA transfer with instruction to DMA Start address Number of bytes to transfer DMA Becomes master of data path (X-Bus to Bus Controller to Memory Bus) Transfers data between RAM and peripheral device IRQ at end of transfer CPU takes back control of the bus

35 35 Overview of PCI Bus

36 36 Review of Bus Evolution In ISA standard CPU talks to cache via local bus Cache talks to memory via memory bus CPU talks to bus adapter via local bus In VESA (Local Bus) standard Extension of ISA: CPU talks directly to graphics via local bus In PCI CPU talks to bus via local bus Bus (PCI bridge) talks to memory Bus talks to main system bus

37 37 PCI Features PCI standardizes: Peripheral I/O bus Memory bus (via bridge) Interrupt and DMA functions provided in bridge PCI peripheral devices can become bus master Expansion bus Fast PCI slots Slower ISA slots (before Pentium 4)

38 38 PCI Bus Speeds Bytes/cycle Bus Clock Transfer Speed Rate PCI MHz 133 MB/s PCI MB/s 66 MHz MB/s MB/s 66 MHz MB/s PCI-X MB/s 133 MHz GB/s MHz GB/s MHz GB/s Memory bus can multiply PCI rate for faster speeds Peripheral I/O bus can divide PCI rate for slower speeds

39 39 Basic PCI Organization PCI Host-to-Bus Bridge (bus ) ROM RAM CPU PCI (expansion) bus etc audio grap hics network ISA/EISA (Bridge) ISA/EISA bus ISA disk other ISA device

40 40 Accelerated Graphics Port (AGP) PCI Host-to-Bus Bridge (bus ) ROM RAM Dedicated path from PCI Bridge to display card CPU etc audio PCI (expansion) bus graphics network ISA/EISA (Bridge) Provides 525 MB/s graphics path for a 133 MHz PCI bus AGP at 525 MB/s for 133 MHz PCI ISA disk ISA/EISA bus other ISA device

41 41 System Boot Hardware system is started or reset Processor performs self-check Processor fetches instruction from address FFFF0h Address FFFF0h must point to ROM Address FFFF0h must contain a JMP instruction Target of JMP must be BIOS (in ROM) BIOS = BASIC INPUT/OUTPUT SYSTEM BIOS begins loading of Operating System ROM = Read Only Memory E 2 PROM = Electronically Erasable Programmable ROM

42 42 Basic Input/Output System (BIOS) Specific to individual computer hardware Provided by Chipset manufacturer Contains default hardware-dependent drivers Console display and keyboard (CON) Line printer (PRN) Auxiliary device (AUX) Date and time (CLOCK$) Boot disk device (block device)

43 43 Device Drivers Software routines for hardware devices Devices are controlled by electrical signals Device s convert received digital codes to electrical signals Device drivers convert user instructions into digital codes Device driver provides user with a standard interface of instructions Processor Instruction Device Controller Code Sequence Device

44 44 Device Drivers User program makes call to OS example: read file OS converts system call to instruction sequence Read file = open buffer, locate file on medium, go to sector, while not EOF {read byte to buffer} Driver converts instruction sequence to code sequence Read byte = 79 3F Processor sends code to and receives replies Read byte: OUT disk_port, 79 OUT disk_port, 3F IN disk_port, byte

45 45 Driver Types Resident Drivers built into the BIOS Installable Installed at System boot time Application run time Processes under UNIX/Linux DEVICE commands in CONFIG.SYS file (DOS) DLLs and VxDs under Windows