L12: I/O Systems. Name: ID:

Transcription

1 L12: I/O Systems Name: ID:

2 Synchronous and Asynchronous Buses Synchronous Bus (e.g., processor-memory buses) Includes a clock in the control lines and has a fixed protocol for communication that is relative to the clock Asynchronous Bus (e.g., I/O buses) It is not clocked, so requires a handshaking protocol and additional control lines (,, Rdy)

3 Synchronous and Asynchronous Buses Synchronous Bus (e.g., processor-memory buses) Includes a clock in the control lines and has a fixed protocol for communication that is relative to the clock Involves very little logic and can run very fast Asynchronous Bus (e.g., I/O buses) It is not clocked, so requires a handshaking protocol and additional control lines (,, Rdy)

4 Synchronous and Asynchronous Buses Synchronous Bus (e.g., processor-memory buses) Includes a clock in the control lines and has a fixed protocol for communication that is relative to the clock Involves very little logic and can run very fast Every device communicating on the bus must use same clock rate To avoid clock skew, they cannot be long if they are fast Asynchronous Bus (e.g., I/O buses) It is not clocked, so requires a handshaking protocol and additional control lines (,, Rdy)

5 Synchronous and Asynchronous Buses Synchronous Bus (e.g., processor-memory buses) Includes a clock in the control lines and has a fixed protocol for communication that is relative to the clock Involves very little logic and can run very fast Every device communicating on the bus must use same clock rate To avoid clock skew, they cannot be long if they are fast Asynchronous Bus (e.g., I/O buses) It is not clocked, so requires a handshaking protocol and additional control lines (,, Rdy) Can accommodate a wide range of devices and device speeds Can be lengthened without worrying about clock skew

6 Synchronous and Asynchronous Buses Synchronous Bus (e.g., processor-memory buses) Includes a clock in the control lines and has a fixed protocol for communication that is relative to the clock Involves very little logic and can run very fast Every device communicating on the bus must use same clock rate To avoid clock skew, they cannot be long if they are fast Asynchronous Bus (e.g., I/O buses) It is not clocked, so requires a handshaking protocol and additional control lines (,, Rdy) Can accommodate a wide range of devices and device speeds Can be lengthened without worrying about clock skew Slow(er) More complex due to handshaking protocol

7 Rdy 1. I/O device requests by raising & putting on the lines

8 Rdy 2 1. I/O device requests by raising & putting on the lines 2. Memory sees, reads from lines, and raises

9 Rdy 3 1. I/O device requests by raising & putting on the lines 2. Memory sees, reads from lines, and raises 3. I/O device sees and releases the and lines

10 4 Rdy 1. I/O device requests by raising & putting on the lines 2. Memory sees, reads from lines, and raises 3. I/O device sees and releases the and lines 4. Memory sees go low and drops

11 5 Rdy 1. I/O device requests by raising & putting on the lines 2. Memory sees, reads from lines, and raises 3. I/O device sees and releases the and lines 4. Memory sees go low and drops 5. When memory ready, putting on lines & raises Rdy

12 6 Rdy 1. I/O device requests by raising & putting on the lines 2. Memory sees, reads from lines, and raises 3. I/O device sees and releases the and lines 4. Memory sees go low and drops 5. When memory ready, putting on lines & raises Rdy 6. I/O device sees Rdy, reads from lines & raises 7. 8.

13 Rdy 7 1. I/O device requests by raising & putting on the lines 2. Memory sees, reads from lines, and raises 3. I/O device sees and releases the and lines 4. Memory sees go low and drops 5. When memory ready, putting on lines & raises Rdy 6. I/O device sees Rdy, reads from lines & raises 7. Memory sees, releases lines, and drops Rdy 8.

14 8 Rdy 1. I/O device requests by raising & putting on the lines 2. Memory sees, reads from lines, and raises 3. I/O device sees and releases the and lines 4. Memory sees go low and drops 5. When memory ready, putting on lines & raises Rdy 6. I/O device sees Rdy, reads from lines & raises 7. Memory sees, releases lines, and drops Rdy 8. I/O device sees Rdy go low and drops