Unit 5. Memory and I/O System

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1 Unit 5 Memory and I/O System 1

2 Input/Output Organization 2

3 Overview Computer has ability to exchange data with other devices. Human-computer communication Computer-computer communication Computer-device communication 3

4 Accessing I/O Devices 4

5 Single Bus Processor Memory Bus I/O device 1 I/O device n Figure 4.1. A single-bus structure. 5

6 Memory-Mapped I/O When I/O devices and the memory share the same address space, the arrangement is called memorymapped I/O Any machine instruction that can access memory can be used to transfer data to or from an I/O device. Move DATAIN, R0 (DATAIN is the I/P buffer) Move R0, DATAOUT (DATAOUT is O/P buffer) Some processors have special In and Out instructions to perform I/O transfer- they support I/O mapped I/O 6

7 Interface Bus Address line Data lines Control lines Address decoder Control circuits Data and status registers I/O interface Input device Figure 4.2. I/O interface for an input device. 7

8 Program-Controlled I/O I/O devices operate at speeds that are vastly different from that of the processor Keyboard, for example, is very slow An Instruction that reads a character from keyboard must be executed only when the character is available in the input buffer of the keyboard interface; also, this character must be read only once The basic idea is to set a status flag, SIN, as part of the status register SIN flag is set to 1 when a character is entered at the keyboard, and cleared to 0 once the character is read by processor 8

9 Program-Controlled I/O (contd..) By checking the SIN flag the software can ensure that it is always reading valid data This is usually done in a program loop that repeatedly reads status register and checks the state of SIN When SIN becomes 1, the program reads the input data register Similar procedure is used for output operation using an output status flag SOUT 9

10 Keyboard Control Example DATAIN DATAOUT STATUS DIRQ KIRQ SOUT SIN CONTROL DEN KEN Figure 4.3. Registers in keyboard and display interf aces. 10

11 Keyboard Control Example Move #LINE,R0 Initialize memory pointer. WAITK TestBit #0,STATUS Test SIN. Branch=0 WAITK Wait for characterto be entered. Move DATAIN,R1 Readcharacter. WAITD TestBit #1,STATUS Test SOUT. Branch=0 WAITD Wait for display to becomeready. Move R1,DATAOUT Sendcharacterto display. Move R1,(R0)+ Store characterandadvance pointer. Compare #$0D,R1 Check if Carriage Return. Branch 0 WAITK If not, get anothercharacter. Move #$0A,DATAOUT Otherwise,sendLine Feed. Call PROCESS Call a subroutineto process the input line. Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the display. 11

12 Three Major Mechanisms Program-controlled I/O processor polls the device Interrupt driven I/O device interrupts processor when ready Direct Memory Access (DMA) 12

13 Interrupts 13

14 Overview In program-controlled I/O, the program enters a wait loop in which it repeatedly tests the device status During the period, the processor is not performing any useful computation However, in many situations other tasks can be performed while waiting for an I/O device to become ready Let the device alert the processor when it becomes ready 14

15 Overview (contd..) This can be done by device sending a hardware signal called an interrupt to the processor One line in the control bus called interruptrequest line is dedicated for this purpose Since the processor is no longer required to continuously check the status of external devices, it can use the waiting period to perform other useful functions 15

16 Example Consider a task that requires some computations to be performed and the results to be printed on line printer repeatedly Assume the program has two routines COMPUTE and PRINT COMPUTE produces a set of n lines of output, to be printed on printer The task can be performed by repeatedly executing first the COMPUTE routine and then the PRINT routine Printer accepts only one line of text at a time 16

17 Example COMPUTE produces first n lines of text; PRINT sends the first line to the printer; then PRINT is suspended; COMPUTE continues to perform other computations; After the printer finishes printing the first line, it send an interrupt-request signal to the processor; In response, the processor interrupts execution of COMPUTE and transfers control to PRINT to send the next line; COMPUTE resumes; 17

18 Example Program 1 COMPUTE routine Program 2 PRINT routine 1 2 Interrupt occurs here i i + 1 M Figure 4.5. Transfer of control through the use of interrupts. 18

19 Several Points Interrupt-service routine PRINT Store the current PC and PSW Return-from-interrupt Interrupt-acknowledge signal Interrupt latency (time between receipt of interrupt request and start of interrupt service routine) Difference between an interrupt-service routine and regular subroutine? 19

20 Interrupt Hardware Processor V dd R INTR INTR INTR1 INTR2 INTR n Figure 4.6.An equivalent circuit for an open-drain bus used to implement a common interrupt-request line. 20

21 Enabling and Disabling Interrupts Since the interrupt request can come at any time, it may alter the sequence of events from that envisaged by the programmer Interrupts must be controlled Ignoring an interrupt happens in the previous example after printing the last line of set of n lines, interrupts must be disabled until another set becomes available for printing 21

22 Enabling and Disabling Interrupts (contd..) The interrupt request signal will be active until it learns that the processor has responded to its request. This must be handled to avoid successive interruptions Let the interrupt be disabled/enabled in the interruptservice routine using DI and EI instructions Let the processor automatically disable interrupts before starting the execution of the interrupt-service routine Edge triggered the interrupt handling circuit responds only to the leading edge of the signal 22

23 Summary 1.The device raises an interrupt request 2.The processor interrupts the program currently being executed 3.Interrupts are disabled by changing the control bits in the PSW (except in case of edge-triggered) 4.The device is informed that its request has been recognized, and in response it deactivates the interrupt request signal 5.The action requested by the interrupt is performed by the interrupt service routine 6.interrupts are enabled and execution of interrupted program is resumed 23

24 Handling Multiple Devices How can the processor recognize the device requesting an interrupt? Given that different devices are likely to require different interrupt-service routines, how can the processor obtain the starting address of the appropriate routine in each case? (Vectored interrupts) Should a device be allowed to interrupt the processor while another interrupt is being serviced? (Interrupt nesting) How should two or more simultaneous interrupt requests be handled? (Daisy-chain) 24

25 Vectored Interrupts A device requesting an interrupt can identify itself by sending a special code to the processor over the bus. Interrupt vector 25

26 Interrupt Nesting Simple solution: only accept one interrupt at a time, then disable all others. Problem: some interrupts cannot be held too long. Priority structure Processor INTR1 INTRp Device 1 Device 2 Devicep INTA1 INTA p Priority arbitration circuit Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines. 26

27 Simultaneous Requests Processor INTR INTA Device 1 Device 2 Device n (a) Daisy chain INTR1 Processor INTA1 INTRp Device Device Priority arbitration circuit INTA p Device Device (b) Arrangement of priority groups 27 Figure 4.8. Interrupt priority schemes.

28 Controlling Device Requests Some I/O devices may not be allowed to issue interrupt requests to the processor. At device end, an interrupt-enable bit in a control register determines whether the device is allowed to generate an interrupt request. At processor end, either an interrupt enable bit in the PSW register or a priority structure determines whether a given interrupt request will be accepted. 28

29 Direct Memory Access 29

30 DMA Think about the overhead in both polling and interrupting mechanisms when a large block of data need to be transferred between the processor and the I/O device. A special control unit may be provided to allow transfer of a block of data directly between an external device and the main memory, without continuous intervention by the processor direct memory access (DMA). The DMA controller provides the memory address and all the bus signals needed for data transfer, increment the memory address for successive words, and keep track of the number of transfers. 30

31 DMA Procedure Processor sends the starting address, the number of data, and the direction of transfer to DMA controller. Processor suspends the application program requesting DMA, starts DMA transfer, and starts another program. After the DMA transfer is done, DMA controller sends an interrupt signal to the processor. The processor puts the suspended program in the Runnable state. 31

32 DMA Register Status and control IRQ IE Done R/ W Starting address Word count Figure Registers in a DMA interface. 32

33 System Processor Main memory System bus Disk/DMA controller DMA controller Printer Keyboard Disk Disk Network Interface Figure Use of DMA controllers in a computer system. 33

34 Memory Access Memory access by the processor and the DMA controller are interwoven. DMA device has higher priority. Among all DMA requests, top priority is given to high-speed peripherals. Cycle stealing Block (burst) mode Data buffer Conflicts 34

35 Bus Arbitration The device that is allowed to initiate data transfers on the bus at any given time is called the bus master. Bus arbitration is the process by which the next device to become the bus master is selected and bus mastership is transferred to it. Need to establish a priority system. Two approaches: centralized and distributed 35

36 Centralized Arbitration BBSY Processor BR BG1 DMA controller 1 BG2 DMA controller 2 Figure A simple arrangement for us b arbitration using a daisy cha 36

37 Centralized Arbitration Time BR BG1 BG2 BBSY Bus master Processor DMA controller 2 Processor Figure Sequence of signals during transfer us of bmastership for the devices in Figure

38 Distributed Arbitration V cc ARB3 ARB2 ARB1 ARB0 Start-Arbitration O.C Interface circuit for device A Figure A distributed arbitration scheme. 38

39 Buses 39

40 Overview The primary function of a bus is to provide a communications path for the transfer of data. A bus protocol is the set of rules that govern the behavior of various devices connected to the bus as to when to place information on the bus, assert control signals, etc. Three types of bus lines: data, address, control The bus control signals also carry timing information. Bus master (initiator) / slave (target) 40

41 Synchronous Bus Timing Time Bus clock Address and command Data t 0 t 1 t 2 Bus cycle Figure Timing of an input transfer on a synchronous bus. 41

42 Synchronous Bus Detailed Timing Time Bus clock Seen by master Address and command t AM Data t DM Seen by slave t AS Address and command Data t DS t 0 t 1 t 2 42 Figure A detailed timing diagram for the input transfer of Figure 4.23

43 Multiple-Cycle Transfers Time Clock Address Command Data Slave-ready Figure An input transfer using multiple clock ycles. c 43

44 Asynchronous Bus Handshaking Protocol for Input Operation Address and command Time Master-ready Slave-ready Data t 0 t 1 t 2 t 3 t 4 t 5 Bus cycle Figure Handshake control of data transfer during an input operat 44

45 Asynchronous Bus Handshaking Protocol for Input Operation (contd..) t 0 - Master places address and command information on the bus, all devices decode the information t 1 - master sets the Master-Ready line to 1 to inform the I/O devices that the address and command information is ready ( t 1 -t 0 is to take care of skew) t 2 - the selected slave after decoded the address and command information, performs the required input operation and puts data on data bus 45

46 Asynchronous Bus Handshaking Protocol for Input Operation (contd..) t 3 -slave ready signal arrives at the master, indicating that input data are available on the bus, master strobes data in to input buffer and drops master ready signal t 4 - master removes address and command information from the bus t 5 - when the device interface receives 1 to 0 transition of the master ready signal, it removes the data and the slave ready signal from the bus- this completes input transfer 46

47 Asynchronous Bus Handshaking Protocol for Output Operation Address and command Time Data Master-ready Slave-ready t 0 t 1 t 2 t 3 t 4 t 5 Bus cycle Figure Handshake control of data transfer during an output opera 47

48 Discussion Trade-offs Simplicity of the device interface Ability to accommodate device interfaces that introduce different amounts of delay Total time required for a bus transfer Ability to detect errors resulting from addressing a nonexistent device or from an interface malfunction Asynchronous bus is simpler to design. Synchronous bus is faster. 48

49 Interface Circuits 49

50 Introduction I/O interface consists of circuitry required to connect an I/O device to a computer bus On one side we have the bus signal for address, data and control On the other side we have a data path with its associated controls to transfer data between the interface and the I/O device (port) 50

51 Function of I/O Interface Provide a storage buffer for at least one word of data Contain status flags that can be accessed by the processor to determine whether the buffer is full or empty Contain address-decoding circuitry to determine when it is being addressed by the processor Generate the appropriate timing signals required by the bus control scheme Perform any format conversion that may be necessary to transfer data between the bus and the I/O device 51

52 Parallel Port A parallel port transfers data in the form of a number of bits, typically 8 or 16, simultaneously to or from the device Used for faster communications 52

53 Parallel Port Input Interface (Keyboard to Processor Connection) Data Processor Address R/ W Master-ready Slave-ready DATAIN SIN Input interface Data Valid Encoder and debouncing circuit Keyboard switches Figure Keyboard to processor connection. 53

54 DATAIN D7 Q 7 D 7 Keyboard data D0 Q 0 D 0 Slaveready 1 SIN Status flag Valid Readstatus Readdata R/W Master- ready A31 Address decoder A1 A0 Figure Input interface circuit. 54

55 Parallel Port Input Interface (Keyboard to Processor Connection) 55

56 Parallel Port Output Interface (Printer to Processor Connection) Data Address DATAOUT Data Processor CPU R/ W SOUT Valid Printer Master-eady Slave-ready Output interface Idle Figure Printer to processor connection. 56

57 D7 P7 DATAIN D0 P0 DATAOUT Data Direction Register My-address RS2 RS1 RS0 R/W Ready Accept Register select Status and control C1 C2 INTR Figure A general 8-bit parallel interf ace. 57

58 Serial Port A serial port is used to connect the processor to I/O devices that require transmission of data one bit at a time. The key feature of an interface circuit for a serial port is that it is capable of communicating in bit-serial fashion on the device side and in a bit-parallel fashion on the bus side. Capable of longer distance communication than parallel transmission. 58

59 Input shift register Serial input DATAIN D7 D0 My-address DATAOUT RS1 RS0 R/W Ready Chip and register select Output shift register Serial output Accept INTR Status and control Receiving clock Transmission clock Figure A serial interface. 59

60 Standard I/O Interfaces 60

61 Overview The needs for standardized interface signals and protocols. Motherboard Bridge: circuit to connect two buses Expansion bus Industry Standard Architecture (ISA), Peripheral Component Interconnect (PCI), Small Computer System Interface (SCSI), Universal Serial Bus (USB), Integrated Device Electronics (IDE) 61

62 Processor Main memory Processor bus Bridge PCI bus Additional memory SCSI controller Ethernet interface USB controller ISA interface SCSI bus Video IDE disk Disk controller CD-ROM controller CD- Disk 1 Disk 2 ROM K eyboard Game Figure An example of a computer system using different interface standards. 62

Chapter 5 Input/Output Organization. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 5 Input/Output Organization Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Accessing I/O Devices Interrupts Direct Memory Access Buses Interface