Chapter 8. Input Output Organization

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Griselda Hope Hopkins
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1 Chapter 8 Input Output Organization 8.1 Introduction: In the design of a simple computer, we assumed one input device and one output device transferring data in and out of the accumulator using a programmed I/O mode. An actual computer system, however, consists of several input and output devices or peripherals. Although the programmed I/O mode can be used in such an environment, it is slow and may not be suitable, especially when the machine is used as a real-time processor responding to irregular changes in the external environment. Consider the example of a processor used to monitor the condition of a patient in a hospital. Although the majority of its patient data gathering operations can be performed in a programmed I/O mode, alarming conditions such as abnormal blood pressure or temperature occur irregularly, and detection of such events requires that the processor be interrupted by the event from its regular activity. We discuss the general concept of interrupt processing and interrupt-driven I/O in this chapter. The transfer of information between the processor and a peripheral consists of the following steps: 1. Selection of the device and checking the device for readiness 2. Transfer initiation, when the device is ready 3. Information transfer 4. Conclusion These steps can be controlled by the processor or the peripheral or both. Contingent upon where the transfer control is located, three modes of I/O are possible. They are, 1. Programmed I=O 2. Interrupt mode I=O 3. Direct memory access (DMA) We will discuss each of these modes in detail following a discussion of the general I/O model. Pertinent details of I/O structures of some popular computer systems are provided as examples. These steps can be controlled by the processor or the peripheral or both. Contingent upon where the transfer control is located, three modes of I/O are possible. They are, 1. Programmed I=O 2. Interrupt mode I=O 3. Direct memory access (DMA) The I/O structure of ASC (American standard code) with one input device and one output device is show n in. ASC communicates with its peripherals thro ugh datainput lines (DIL) and data-out put lines (DOL). There are two control lines: input and output. The data flip-flop in the control unit is used to coordinate the I/O activities. In the structure shown in Figure X1, the memory is interfaced to the central processing unit (CPU) through a memory bus (consisting of address, data, and control=status lines), and the peripherals communicate with the CPU over the I/O bus. Thus there is a memory address space and a separate I=O address space. The system is said to use the isolated I/O mode. This mode of I/O requires a set of instructions dedicated for I/O operations. In some systems, both the memory and I/O devices are connected to the CPU through the same bus, as shown in Figure X2.

2 In this structure, the device addresses are a part of the memory address space. Hence, the load and store instructions used with memory operands can be used as the read and write instructions with respect to those addresses configured for I/O devices. This mode of I/O is known as memory-mapped I/O. The advantages of memorymapped I/O is that separate I/O instructions are not needed; the disadvantages are that some of the memory address space is used up by the I/O, and it can be difficult to distinguish between the memory and I/O-oriented operations in a program. Program I/O (Mode of Transfer): The major functions of a device interface are 1. Timing: (Asynchronous/synchronous Data Transfer) 2. Control 3. Data conversion 4. Error detection and correction The timing and control aspects correspond to the manipulation of control and status signals to bring about the data transfer. In addition, the opera ting speed Difference between the CPU and the device must be compensated for by the interface.in general; data conversion from one code to the other is needed, since each device (or the medium on which data are represented) may use a different code to

3 represent data. Errors occur during transmission and must be detected and if possible corrected by the interface. 1. Timing: Asynchronous Data Transfer (Handshaking) So far in this chapter, we have assumed that the CPU controls the bus: In-general, when several devices are connected to the bus, it is possible that a device other than the CPU can become bus master. Thus, among the two devices involved in the data transfer on the bus, one will be the bus master and the other will be the slave. The data transfer on a bus between two devices can be either synchronous or asynchronous. Figure X3 shows the timing diagrams for an asynchronous transfer between the source and destination devices. In Figure X3(a), the source initiates the transfer by placing data on the bus and setting DATA READY. The destination ACKs, in response to which the DATA READY signal is removed, after which the ACK is removed. Note that the data are removed from the bus only after the ACK is received. In Figure X3(b) the destination device initiates (i.e. requests) the transfer, in response to which the source puts the data on the bus. The acknowledge sequence is the same as in Figure X3(a) Peripheral devices usually operate in an asynchronous mode with respect to the CPU because they are not usually controlled by the same clock that controls the CPU. The sequence of event s required to bring about the data transfer between two devices is called the protocol or the handshake.

4 2. Control: During the data-transfer handshake, some events are brought about by the bus master and some are brought about by the slave device. The data transfer is completely controlled by the CPU in the program med I/O mode. A typical protocol for this mode of I/O is shown in Table T1. We have combined the protocols for both input and output operations. A device will be either in the input or the output mode at any given time. This sequence repeats for each transfer. The speed difference between the CPU and the device renders this mode of I/O inefficient. An alternative is to distribute part of the control activities to the device controller. Now, the CPU sends a command to the device controller to input or output data and continues its processing activity. The controller collects the data from (or sends data to) the device and interrupts the CPU. The CPU disconnects the device after the data transfer is complete (i.e., the CPU services the interrupt) and

5 returns to the mainline processing from which it was interrupted. A typical sequence of events during an interrupt-mode I/O is shown in Table T2. The protocol assumes that the CPU always initiates the data transfer. In practice, a peripheral device may first interrupt the CPU, and the type of transfer (input or output) is determined during the CPU peripheral handshake. The data input need not be initiated only by the CPU. Interrupt mode I/O reduces the CPU wait time (for the slow device) but requires a more complex device controller than that in the programmed I/O mode. The causes of interrupt and the popular interrupt structures are discussed in the next section. In addition to the earlier protocol s, other control and timing issues are introduced by the characteristics of the link (i.e., the data line or lines that connect the device and the CPU). The data link can be simplex (unidirectional), half duplex (either direction, one way at a time), full duple x (both direct ions simultaneously), serial, or parallel. Serial transmission require s that a constant clock rate be maintained throughout data transmission to avoid synchronization problems; in parallel transmission, care must be taken to avoid data skewing (i.e., data arriving at different time s on the bus lines due to different electrical characteristics of individual bit lines). Data transfer between peripheral devices located in the vicinity of the CPU is usually performed in parallel mode, while the remote devices communicate with the CPU in serial mode. We will assume parallel mode transfer in the following sections. 3. Data Conversion: The data representation on the I/O medium is unique to each medium. For example, a magnetic tape uses either ASCII or EBCDIC code to represent data. Internally, the CPU might use a binary or BCD (decimal) representation. In addition, the interface link might be organized as serial-by-bit, serial-by-character (quasiparallel), or serial-by-word (fully parallel). Thus, two levels of data conversion are to be accomplished by the interface: conversion from peripheral to link format and from link to CPU format. 4. Error Detecting and Correcting Code: Errors may occur whenever data are transmitted between two devices. One or more extra bits known as parity bits are used as part of the data representation to facilitate error detection and correction. Such parity bits, if not already present in the data, are included into the data stream by the interface before transmission and checked at the destination. Depending on the number of parity bits, various levels of error detection and correction are possible. Error detection and correction are particularly important in I/O because the peripheral devices exposed to the external environment are error prone. Errors may be due to mechanical wear, temperature and humidity variations, mismounted storage media, circuit drift, incorrect data-transfer sequences (protocols), and the like. Figure X4(a) shows a parity bit included into a data stream of 8 bits. The parity bit P is 1 if odd parity is used (the total number of 1s is odd) and 0 if even parity is used (the total number of 1s is even). When this 9-bit data word is transmitted, the receiver of the data computes the parity bit. If P matches the

6 computed parity, there is no error in transmission; if an error is detected, the data can be retransmitted. Figure :X4 Parity scheme for a magnetic tape. An extra track (track 8) is added to the tape format. The parity track stores the parity bit for each character represented on the eight tracks of the tape. At the end of a record, a longitudinal parity character consisting of a parity bit for each track is added. More elaborate error detection and correction schemes are often used. Interrupt- initiated I/O: In a number of conditions the processor may be interrupted from its normal processing activity. Some of the conditions are, 1. Power failure as detected by a sensor 2. Arithmetic conditions such as overflow and underflow 3. Illegal data or illegal instruction code 4. Errors in data transmission and storage 5. Software-generated interrupts (as intended by the user) 6. Normal completion of an asynchronous transfer In each of these conditions, the processor must discontinue its processing activity, attend to the interrupting condition, and (if possible) resume the processing activity from where it had been when the interrupt occurred. In order for the processor to be able to resume normal processing after servicing the interrupt, it is essential to at least save the address of the instruction to be executed just before entering the interrupt

7 service mode. In addition, contents of the accumulator and all other registers must be saved. Typically, when an interrupt is received, the processor completes the current instruction and jumps to an interrupt service routine. An interrupt service routine is a program preloaded into the machine memory that performs the following functions: 1. Disables further interrupts (temporarily) 2. Saves the processor status (all registers) 3. Enables further interrupts 4. Determines the cause of interrupt 5. Services the interrupt 6. Disables interrupts 7. Restores processor status 8. Enables further interrupts 9. Returns from interrupt The processor disables further interrupts just long enough to save the status, since a proper return from interrupt service routine is not possible if the status is not completely saved. The processor status usually comprises the contents of all the registers, including the program counter and the program status word. Servicing the interrupt simply means taking care of the interrupt condition: in the case of an I/O interrupt, it corresponds to data transfer; in case of power failure, it is the saving of registers and status for normal resumption of processing when the power is back; during an arithmetic condition, it is checking the previous operation or simply setting a flag to indicate the arithmetic error. Once the interrupt service is complete, the processor status is restored. That is, all the registers are loaded with the values saved during step 2. Interrupt s are disabled during this restore period. This completes the interrupt service, and the processor returns to the norm al processing mode. Direct Memory Access (DMA): The programmed and interrupt mode I/O structures transfer data from the device into or out of a CPU register (accumulator in ASC). If the amount of data to be transferred is large, these schemes would overload the CPU. Data are normally required to be in the memory, especially when voluminous, and some complex computations are to be performed on them. A DMA scheme enables a device controller to transfer data directly into or from main memory. The majority of datatransfer control operations are now performed by a device controller. CPU initiates the transfer by commanding the DMA device to transfer the data and then continues with its processing activities. The DMA device performs the data transfer and interrupts the CPU only when it is completed. Figure X5 shows a DMA transfer structure. The DMA device (either a DMA controller or a DMA channel) is a limited-capability processor. It will have a word count register (WCR), an address register, and a data buffer. To start a transfer, the CPU initializes the address register (AR) of the DMA channel with the memory address from (or to) which the data must be transferred and the WCR with the number of units of data (words or bytes) to be transferred. Note that the data bus is connected to these two registers. Usually, these registers are addressed by the CPU as output devices using the address bus; the initial values are transferred into them via the data bus. The DMA controller can decrement WCR and increment AR for each word

8 transferred. Assuming an input transfer, the DMA controller starts the input device and acquires the data in its buffer register. This word is then transferred into the memory location addressed by AR; that is, MAR AR: MBR Data buffer, WRITE MEMORY: These transfers are done using the address and data buses. In this scheme, the CPU and the DMA device controller both try to access the memory through MAR and MBR. Since the memory cannot be simultaneously accessed both by the DMA and the CPU, a priority scheme is used to prohibit CPU from accessing the memory during a DMA operation. That is, a memory cycle is assigned to the DMA device for the transfer of data during which the CPU is prevented from accessing memory. This is called cycle stealing, since the DMA device steals a memory cycle from the CPU when it is required to access the memory. Once the transfer is complete, the CPU can access the memory. The DMA controller decrements the WCR and increments AR in preparation for the next transfer. When WCR reaches 0, a transfercomplete interrupt is sent to the CPU by the DMA controller. Figure X6 shows the sequence of events during a DMA transfer. DMA devices always have higher priority than the CPU for memory access because the data available in the device buffer may

9 be lost if not transferred immediately. Hence, if an I/O device connected via DMA is fast enough, it can steal several consecutive memory cycles, thus holding back the CPU from accessing the memory for several cycles. If not, the CPU will access the memory in between each DMA transfer cycle. Figure : X6 DMA cont rollers can be either dedicated to one device or shared among several I/O devices. Figure 7.19 shows a bus structure that enables such a sharing. This bus structure is called compatible I/O bus structure because an I /O device is configured to perform both program med and DMA transfers. DMA channels are shared by all the I/O devices. The I/O device may be transferring data at any time through either program med or DMA path s. Some computer system s use a multiple-bus structure in which some I/O devices are connected to the DMA bus while others communicate with the CPU in a programmed I/O mode.

INPUT-OUTPUT ORGANIZATION

INPUT-OUTPUT ORGANIZATION Peripheral Devices: The Input / output organization of computer depends upon the size of computer and the peripherals connected to it. The I/O Subsystem of the computer, provides