Overcoming System Memory Challenges with Persistent Memory and NVDIMM-P

Transcription

1 Overcoming System Memory Challenges with Persistent Memory and NVDIMM-P JEDEC Server Forum 2017 Bill Gervasi, Discobolus Designs Copyright 2017 Jonathan Hinkle, Lenovo Datacenter Research and Technology

2 Challenges to continuing the trend System memory capacity improvements are slowing Inexpensive bits available with non-volatile memories however performance pales compared with DRAM CPU Memory Memory Memory Memory performance and capacity challenges 3DPC 2DPC 1DPC 2CH/CPU 4CH/CPU 6CH/CPU

3 Implications for datacenter systems Data consumption rates continue to increase dramatically Powerful response needed to meet challenges of big data

4 Features of next generation main memory LATENCY

5 Persistent memory part of the solution I/O CPU Persistent Memory = data guaranteed valid once sent over the memory bus Power fail no longer implies data loss Databases in particular can rethink checkpoint and commit cycles

6 Hybrid Memory Modules and NVDIMM-N NVDIMM-N was JEDEC s introduction of persistent memory Byte-addressable DRAM for lowest latency with NAND for persistence backup Requires an energy source to power memory during backup

7 Limitations of NVDIMM-N NVDIMM-N capacity limited by board space Use in deterministic DDR4 DRAM bus implies direct addressing of only the DRAM part of the module Large non-volatile memory not addressable it only mirrors the DRAM contents However, persistence of memory is an industry changing concept

8 Hybrid Memory Modules and NVDIMM-F NVDIMM-F eliminates DRAM, simply provides NAND storage big bits Block-oriented access only SSD in a memory module Controller NAND Host DDR4 RAS-CAS Interface

9 Limitations of NVDIMM-F NVDIMM-F provides big bits with long NAND latency exposed Caches in main memory required to hide latency, prevents persistence Copying between cache and NAND consumes channel bandwidth However, NVDIMM-F does provide massive amounts of memory not limited to DRAM sizes

10 Coming soon: NVDIMM-P standard Traditional DRAM channel interfaces support only deterministic access and balanced read/write performance NVDIMM-P is a NEW channel protocol to enable the combination of persistence and big bits together Hides latency of media type by: Non-deterministic accesses with out of order completion Speculative read mechanisms Posted store model using write credits Deterministic time slots allows mixing DRAM and NVM on the same channel

11 NVDIMM-P protocol CMD READ READ READ READ DATA HIT HIT HIT MISS Out of order completion allows latency of media to be hidden options defined: Energy source Persistent writes Explicit flushes

12 NVDIMM-P as persistent big bits memory NVDIMM-P allows very large memory capacity modules Supports a variety of media types: NAND, PCM, MRAM, 3DX Supports a variety of cached or non-cached implementations Supports multiple models for data persistence Uses new sideband signals: requires new memory controllers

13 Summary Existing NVDIMM implementations provide exciting new capabilities of & Big bits DRAM channel definition expanded to comprehend heterogenous media types DDR4 bus with NVDIMM-P extensions & DDR5 bus Variety of NVDIMM-P modules coming Media types & Cache sizes and structures NVDIMM-P protocol specification released in 2018

14 Thank you